On 9/15/21 8:31 AM, Martin Liška wrote:
On 9/14/21 09:56, Christophe LYON via Gcc-patches wrote:
So adjustment is needed for both arm and aarch64 targets
Hello.
I noticed the same problem and I've got a patch candidate for it.
What do you think about it?
I've now silenced the warning for internal default values, but they're
still worth discussion.
For arm, I think it would make sense to use 32 for constructive for the
generic target, but perhaps we think the older chips aren't worth
constraining new code for? In which case, perhaps
param_l1_cache_line_size should also default to 64 for the generic target.
For aarch64, it seems even more questionable that
param_l1_cache_line_size is 32 for the generic target; are there any
aarch64 CPUs with a 32B L1 cache line?
Jason
