Hi!

On Wed, Aug 11, 2021 at 11:02:25AM -0500, Pat Haugen wrote:
>       * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add new flag.
>       (POWERPC_MASKS): Likewise.

"Add OPTION_MASK_P10_FUSION_2STORE", instead.

> +static bool
> +is_fusable_store (rtx_insn *insn, rtx *str_mem)
> +{
> +  /* Insn must be a non-prefixed base+disp form store.  */
> +  if (is_store_insn (insn, str_mem)
> +      && get_attr_prefixed (insn) == PREFIXED_NO
> +      && get_attr_update (insn) == UPDATE_NO
> +      && get_attr_indexed (insn) == INDEXED_NO)
> +    {
> +      /* Further restictions by mode and size.  */

(typo, "restrictions")

> +      machine_mode mode = GET_MODE (*str_mem);
> +      HOST_WIDE_INT size;
> +      if (MEM_SIZE_KNOWN_P (*str_mem))
> +     size = MEM_SIZE (*str_mem);
> +      else
> +     return false;

      if (!MEM_SIZE_KNOWN_P (*str_mem))
        return false;

      machine_mode mode = GET_MODE (*str_mem);
      HOST_WIDE_INT size = MEM_SIZE (*str_mem);

> +static int
> +power10_sched_reorder (rtx_insn **ready, int lastpos)
> +{
> +  rtx mem1;
> +
> +  /* Do store fusion during sched2 only.  */
> +  if (!reload_completed)
> +    return cached_can_issue_more;

Should that just be "return false"?

> +    {
> +      int pos;
> +      rtx mem2;
> +
> +      /* A fusable store was just scheduled.  Scan the ready list for another
> +      store that it can fuse with.  */
> +      pos = lastpos;

Declare the var not before here?

> +      while (pos >= 0)
> +     {

And mem2 not before in this block?

> +/* { dg-final { scan-assembler-times {stw 4,4\(3\)\n\tstw 6,8\(3\)} 1 { 
> target lp64 } } } */
> +/* { dg-final { scan-assembler-times {stw 4,4\(3\)\n\tstw 6,8\(3\)} 2 { 
> target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {std 4,8\(3\)\n\tstd 6,16\(3\)} 1 { 
> target lp64 } } } */
> +/* { dg-final { scan-assembler-times {stfd 1,8\(3\)\n\tstfd 3,16\(3\)} 1 } } 
> */

This is probably okay because p10 is not supported on any config that
uses register names.

> +/* { dg-final { scan-assembler-not {stw 4,4\(3\)\n\tstw 6,8\(3\)} } } */
> +/* { dg-final { scan-assembler-not {std 4,8\(3\)\n\tstd 6,16\(3\)} { target 
> lp64 } } } */
> +/* { dg-final { scan-assembler-not {stfd 1,8\(3\)\n\tstfd 3,16\(3\)} } } */

Heh.  A little fragile, the compiler could reorder the stores for other
reasons, but the best we can do here I guess.

Okay for trunk with the trivial cleanups.  Thanks!


Segher

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