"bin.cheng via Gcc-patches" <gcc-patches@gcc.gnu.org> writes: > Hi, > When playing with std::experimental::simd, I found a bug newly introduced in > AArch64 backend. As commit message describes: > 7 Pattern "*extend<SHORT:mode><GPI:mode>2_aarch64" is duplicated > 8 from the corresponding zero_extend pattern, however %<w> needs > 9 to be expanded according to its mode iterator because the smov > 10 instruction is different to umov. > > Without the fix, it forces expanding to w register no matter the mode is. > This simple patch fixes the issue which should be obvious. > > Bootstrap and test on AArch64. Any comments? > > Thanks, > bin > > aarch64: Expand %<w> correctly according to mode iterator > > Pattern "*extend<SHORT:mode><GPI:mode>2_aarch64" is duplicated > from the corresponding zero_extend pattern, however %<w> needs > to be expanded according to its mode iterator because the smov > instruction is different to umov. > > 2021-07-28 Bin Cheng <bin.ch...@linux.alibaba.com> > > gcc/ > * config/aarch64/aarch64.md > (*extend<SHORT:mode><GPI:mode>2_aarch64): Use %<GPI:w>0.
OK, thanks. Richard > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index eb8ccd4b97b..7085cd4a51d 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -1880,7 +1880,7 @@ > "@ > sxt<SHORT:size>\t%<GPI:w>0, %w1 > ldrs<SHORT:size>\t%<GPI:w>0, %1 > - smov\t%w0, %1.<SHORT:size>[0]" > + smov\t%<GPI:w>0, %1.<SHORT:size>[0]" > [(set_attr "type" "extend,load_4,neon_to_gp") > (set_attr "arch" "*,*,fp")] > )
