Hi, V2 of this patch uses the same approach as that just implemented for the multiply high-half cost patch.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-07-28 Jonathan Wright <jonathan.wri...@arm.com>
* config/aarch64/aarch64.c: Traverse RTL tree to prevent cost
of vec_select high-half from being added into Neon add cost.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vaddX_high_cost.c: New test.
From: Jonathan Wright
Sent: 29 July 2021 10:22
To: gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>
Cc: Richard Sandiford <richard.sandif...@arm.com>; Kyrylo Tkachov
<kyrylo.tkac...@arm.com>
Subject: [PATCH] aarch64: Don't include vec_select high-half in SIMD add cost
Hi,
The Neon add-long/add-widen instructions can select the top or bottom
half of the operand registers. This selection does not change the
cost of the underlying instruction and this should be reflected by
the RTL cost function.
This patch adds RTL tree traversal in the Neon add cost function to
match vec_select high-half of its operands. This traversal prevents
the cost of the vec_select from being added into the cost of the
subtract - meaning that these instructions can now be emitted in the
combine pass as they are no longer deemed prohibitively expensive.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-07-28 Jonathan Wright <jonathan.wri...@arm.com>
* config/aarch64/aarch64.c: Traverse RTL tree to prevent cost
of vec_select high-half from being added into Neon add cost.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/vaddX_high_cost.c: New test.
rb14710.patch
Description: rb14710.patch
