Hi,
For instructions like cvtss2si, there is no need to output the 'l'
or 'q' suffixes just like cvtss2usi, since the output operand is always
register and those suffixes are only used to distinguish ambiguous
memory operands.
Bootstraped and regression tested on x86_64-linux-gnu {,-m32}.
OK for master?
gcc/ChangeLog:
* config/i386/i386.md (fix_trunc<MODEF:mode><SWI48:mode>_sse):
Remove <SWI48:rex64suffix> in output template.
* config/i386/sse.md: (sse_cvtss2si<rex64namesuffix>_2):
Remove <rex64suffix> in output template.
(sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Likewise.
(sse2_cvtsd2si<rex64namesuffix><round_name>): Likewise.
(sse2_cvtsd2si<rex64namesuffix>_2): Likewise.
(sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512f-vcvtsd2si-1.c: Adjust output scan.
* gcc.target/i386/avx512f-vcvtsd2si64-1.c: Likewise.
* gcc.target/i386/avx512f-vcvtss2si-1.c: Likewise.
* gcc.target/i386/avx512f-vcvtss2si64-1.c: Likewise.
* gcc.target/i386/avx512f-vcvttsd2si-1.c: Likewise.
* gcc.target/i386/avx512f-vcvttsd2si64-1.c: Likewise.
* gcc.target/i386/avx512f-vcvttss2si-1.c: Likewise.
* gcc.target/i386/avx512f-vcvttss2si64-1.c: Likewise.
---
gcc/config/i386/i386.md | 2 +-
gcc/config/i386/sse.md | 12 ++++++------
gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c | 4 ++--
.../gcc.target/i386/avx512f-vcvtsd2si64-1.c | 4 ++--
gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c | 4 ++--
.../gcc.target/i386/avx512f-vcvtss2si64-1.c | 4 ++--
gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c | 4 ++--
.../gcc.target/i386/avx512f-vcvttsd2si64-1.c | 4 ++--
gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c | 4 ++--
.../gcc.target/i386/avx512f-vcvttss2si64-1.c | 4 ++--
10 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 156c6a94989..55e0b3ff507 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4751,7 +4751,7 @@ (define_insn "fix_trunc<MODEF:mode><SWI48:mode>_sse"
(fix:SWI48 (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode)
&& (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "%vcvtt<MODEF:ssemodesuffix>2si<SWI48:rex64suffix>\t{%1, %0|%0, %1}"
+ "%vcvtt<MODEF:ssemodesuffix>2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "maybe_vex")
(set (attr "prefix_rex")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index bcf1605d147..8c7582ed277 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5413,7 +5413,7 @@ (define_insn "sse_cvtss2si<rex64namesuffix><round_name>"
(parallel [(const_int 0)]))]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE"
- "%vcvtss2si<rex64suffix>\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
+ "%vcvtss2si\t{<round_op2>%1, %0|%0, %k1<round_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
@@ -5426,7 +5426,7 @@ (define_insn "sse_cvtss2si<rex64namesuffix>_2"
(unspec:SWI48 [(match_operand:SF 1 "nonimmediate_operand" "v,m")]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE"
- "%vcvtss2si<rex64suffix>\t{%1, %0|%0, %1}"
+ "%vcvtss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
@@ -5442,7 +5442,7 @@ (define_insn
"sse_cvttss2si<rex64namesuffix><round_saeonly_name>"
(match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>"
"v,<round_saeonly_constraint>")
(parallel [(const_int 0)]))))]
"TARGET_SSE"
- "%vcvttss2si<rex64suffix>\t{<round_saeonly_op2>%1, %0|%0,
%k1<round_saeonly_op2>}"
+ "%vcvttss2si\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
@@ -5857,7 +5857,7 @@ (define_insn "sse2_cvtsd2si<rex64namesuffix><round_name>"
(parallel [(const_int 0)]))]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2"
- "%vcvtsd2si<rex64suffix>\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
+ "%vcvtsd2si\t{<round_op2>%1, %0|%0, %q1<round_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "bdver1_decode" "double,double")
@@ -5871,7 +5871,7 @@ (define_insn "sse2_cvtsd2si<rex64namesuffix>_2"
(unspec:SWI48 [(match_operand:DF 1 "nonimmediate_operand" "v,m")]
UNSPEC_FIX_NOTRUNC))]
"TARGET_SSE2"
- "%vcvtsd2si<rex64suffix>\t{%1, %0|%0, %q1}"
+ "%vcvtsd2si\t{%1, %0|%0, %q1}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
@@ -5887,7 +5887,7 @@ (define_insn
"sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>"
(match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>"
"v,<round_saeonly_constraint2>")
(parallel [(const_int 0)]))))]
"TARGET_SSE2"
- "%vcvttsd2si<rex64suffix>\t{<round_saeonly_op2>%1, %0|%0,
%q1<round_saeonly_op2>}"
+ "%vcvttsd2si\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}"
[(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
index 402af5048f6..40fcb43c3ff 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvtsd2sil?\[
\\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvtsd2sil?\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2si\[
\\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128d x;
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c
index dad26e4b729..c8cc485aeb6 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvtsd2siq\[
\\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvtsd2siq\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2si\[
\\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
index e3f42238097..2b820f050f6 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvtss2sil?\[
\\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvtss2sil?\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2si\[
\\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128 x;
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c
index 86ef95a64fd..6a25bb93e6d 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvtss2siq\[
\\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvtss2siq\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2si\[
\\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtss2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
index e7f23aa7e50..e9b1d9b6c09 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvttsd2sil?\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvttsd2sil?\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2si\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128d x;
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c
index dd06e381a96..fcd45479215 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvttsd2siq\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvttsd2siq\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2si\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
index 859848201a4..7351d33b142 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvttss2sil?\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvttss2sil?\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttss2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttss2si\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128 x;
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c
index 85d5837b1f3..dc7ef3dd648 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -mavx512f" } */
-/* { dg-final { scan-assembler-times "vcvttss2siq\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
-/* { dg-final { scan-assembler-times "vcvttss2siq\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttss2si\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttss2si\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
--
2.18.2
