[wwwdocs] add information on TILE-Gx/TILEPro ports

[Walter Lee]

This patch adds information on the Tile-Gx/TILEPro ports to wwwdocs.  Ok to
commit? (assuming I have commit rights which I have not tried.)

Thanks,

Walter


Index: backends.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v
retrieving revision 1.42
diff -u -p -r1.42 backends.html
--- backends.html       5 Nov 2011 20:55:57 -0000       1.42
+++ backends.html       14 Feb 2012 17:24:36 -0000
@@ -99,6 +99,8 @@ sh       |     Q   CB   qr      da   
 sparc    |     Q   CB   qr p    da   
 spu      |   ? Q  *C       p g bd    
 stormy16 | ???L  FIC D l   p  m  a
+tilegx   |   S Q   C    q  p g bda e
+tilepro  |   S   F C       p g bda e
 v850     | ??    FI       cp gm d   s
 vax      |  M?    I       cp     a e 
 xtensa   |   ?     C       p   bd    
Index: index.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v
retrieving revision 1.833
diff -u -p -r1.833 index.html
--- index.html  12 Feb 2012 18:55:35 -0000      1.833
+++ index.html  14 Feb 2012 17:24:36 -0000
@@ -53,6 +53,11 @@ mission statement</a>.</p>
 
 <dl class="news">
 
+<dt><span>TILE-Gx and TILEPro processor support</span>
+    <span class="date">[2012-02-14]</span></dt>
+<dd>Ports for the TILE-Gx and TILEPro families of processors have been
+contributed by Tilera.</dd>
+
 <dt><span>Atomic memory model support</span>
     <span class="date">[2011-11-06]</span></dt>
 <dd>C++11/C11 <a href="http://gcc.gnu.org/wiki/Atomic/GCCMM";>memory model</a>
Index: readings.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/readings.html,v
retrieving revision 1.216
diff -u -p -r1.216 readings.html
--- readings.html       5 Nov 2011 20:55:57 -0000       1.216
+++ readings.html       14 Feb 2012 17:24:36 -0000
@@ -263,6 +263,16 @@ Intel&reg;64 and IA-32 Architectures Sof
   <br />Acronym stands for: Scalable Processor ARChitecture
  </li>
  
+ <li>tilegx
+  <br />Manufacturer: Tilera
+  <br /><a href="http://www.tilera.com/scm/docs/index.html";>Documentation</a>
+ </li>
+ 
+ <li>tilepro
+  <br />Manufacturer: Tilera
+  <br /><a href="http://www.tilera.com/scm/docs/index.html";>Documentation</a>
+ </li>
+ 
  <li>v850
   <br />Manufacturer: NEC
  </li>
Index: gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.82
diff -u -p -r1.82 changes.html
--- gcc-4.7/changes.html        13 Feb 2012 21:57:31 -0000      1.82
+++ gcc-4.7/changes.html        14 Feb 2012 17:24:37 -0000
@@ -715,6 +715,11 @@ well.</p></li>
         default on UltraSPARC T3 (Niagara 3) and later CPUs.</li>
   </ul>
 
+<h3>TILE-Gx/TILEPro</h3>
+  <ul>
+    <li>Support has been added for the Tilera TILE-Gx and TILEPro families of
+      processors.</li>
+  </ul>
 
 <!--
 <h2>Documentation improvements</h2>