On Thu, Jun 17, 2021 at 06:56:09PM -0400, Michael Meissner wrote: > The 'lp64' test > was needed because big endian 32-bit code cannot enable the IEEE 128-bit > floating point instructions.
No, *does not* enable them. After diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 2c249e186e1e..d4aac4164cfe 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4281,7 +4281,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW; } - if (TARGET_FLOAT128_HW && !TARGET_64BIT) + if (0&& TARGET_FLOAT128_HW && !TARGET_64BIT) { if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0) error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64"); you can compile fine with -m32 if you add -mfloat128-hardware as well (it is disabled for BE as well, that should be fixed as well a few lines up from there). Can you show any code that will not work please? Not allowing QP float with -m32 causes many more problems than just allowing it would. > * gcc.target/powerpc/float128-minmax.c: Adjust expected code for > power10. > * lib/target-supports.exp (check_effective_target_has_arch_pwr10): > New target support. Just "New." please. > /* { dg-require-effective-target powerpc_p9vector_ok } */ Please try whether you can lose that line as well. Okay for trunk, and for 11 after the usual soak. Thanks! Segher