[PATCH] aarch64: Model zero-high-half semantics of ADDHN/SUBHN instructions

Tue, 15 Jun 2021 03:02:41 -0700 

Hi,

As subject, this patch models the zero-high-half semantics of the
narrowing arithmetic Neon instructions in the
aarch64_<sur><addsub>hn<mode> RTL pattern. Modeling these
semantics allows for better RTL combinations while also removing
some register allocation issues as the compiler now knows that the
operation is totally destructive.

Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-06-14  Jonathan Wright  <jonathan.wri...@arm.com>

        * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>):
        Change to an expander that emits the correct instruction
        depending on endianness.
        (aarch64_<sur><addsub>hn<mode>_insn_le): Define.
        (aarch64_<sur><addsub>hn<mode>_insn_be): Define.

Attachment: rb14566.patch
Description: rb14566.patch

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