On Thu, Jun 10, 2021 at 02:28:34PM -0500, Peter Bergner via Gcc-patches wrote: > On 6/7/21 2:00 PM, Jeff Law wrote: > > I can't divulge many of the details right now, but one of the quirks of our > > architecture is that reg+d addressing modes for our vector loads/stores > > require > > the displacement to be aligned. This is an artifact of how these > > instructions > > are encoded. > > Given what you're describing, it sounds like POWER has something similar. > Our reg+displacement addressing uses 16-bit displacements using D, DS or DQ > operand fields. The D field encodes the entire 16-bits, but the DS and DQ > fields only encode 14-bits and 12-bits respectively.
Yes, the low 2 resp. 4 bits of the offset are used for other things in the instruction encoding for DS and DQ. > The DS and DQ operands > have the same maximum displacement as D operands, we just force that their > bottom 2-bits/4-bits must be zero, so we don't need to include them in the > insn encoding. I believe this is all just handled in our legitimate address > routines, but maybe Segher and/or Mike can correct me if I'm wrong? This is all correct. But probably the main thing is that our ABIs require most things to be naturally aligned (up to 16 bytes). The machines do not require that (anymore), but requiring this in the ABI still is a performance win afaics (and a lot easier for (compiler) implementers -- most issues you describe just disappear ;-) ) Something tells me this won't work for you though? Segher
