Hi,
As mentioned in PR, for following test-case:
#include <arm_neon.h>
uint32x2_t f1(float32x2_t a, float32x2_t b)
{
return vabs_f32 (a) >= vabs_f32 (b);
}
uint32x2_t f2(float32x2_t a, float32x2_t b)
{
return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
}
We generate vacge for f2, but with -ffast-math, we generate following for f1:
f1:
vabs.f32 d1, d1
vabs.f32 d0, d0
vcge.f32 d0, d0, d1
bx lr
This happens because, the middle-end inverts the comparison to b <= a,
.optimized dump:
_8 = __builtin_neon_vabsv2sf (a_4(D));
_7 = __builtin_neon_vabsv2sf (b_5(D));
_1 = _7 <= _8;
_2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
_6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
return _6;
and combine fails to match the following pattern:
(set (reg:V2SI 121)
(neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
(abs:V2SF (reg:V2SF 122)))))
because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
The attached patch adjusts the neon_vca patterns to use GLTE instead
similar to neon_vca<cmp_op><mode>_fp16insn, and removes NEON_VACMP iterator.
Code-gen with patch:
f1:
vacle.f32 d0, d1, d0
bx lr
Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-*-*.
OK to commit ?
Thanks,
Prathamesh
2021-06-01 Prathamesh Kulkarni <prathamesh.kulka...@linaro.org>
PR target/97906
* config/arm/iterators.md (NEON_VACMP): Remove.
* config/arm/neon.md (neon_vca<cmp_op><mode>): Use GLTE instead of GTGE
iterator.
(neon_vca<cmp_op><mode>_insn): Likewise.
(neon_vca<cmp_op_unsp><mode>_insn_unspec): Use NEON_VAGLTE instead of
NEON_VACMP.
testsuite/
* gcc.target/arm/simd/pr97906.c: New test.
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 3042bafc6c6..0e0e825225a 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -364,8 +364,6 @@
(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
UNSPEC_VCLT UNSPEC_VCLE])
-(define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
-
(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
UNSPEC_VCALE UNSPEC_VCALT])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index cc82d068a1c..ccc99603531 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2400,7 +2400,7 @@
(define_expand "neon_vca<cmp_op><mode>"
[(set (match_operand:<V_cmp_result> 0 "s_register_operand")
(neg:<V_cmp_result>
- (GTGE:<V_cmp_result>
+ (GLTE:<V_cmp_result>
(abs:VCVTF (match_operand:VCVTF 1 "s_register_operand"))
(abs:VCVTF (match_operand:VCVTF 2 "s_register_operand")))))]
"TARGET_NEON"
@@ -2419,7 +2419,7 @@
(define_insn "neon_vca<cmp_op><mode>_insn"
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
(neg:<V_cmp_result>
- (GTGE:<V_cmp_result>
+ (GLTE:<V_cmp_result>
(abs:VCVTF (match_operand:VCVTF 1 "s_register_operand" "w"))
(abs:VCVTF (match_operand:VCVTF 2 "s_register_operand" "w")))))]
"TARGET_NEON && flag_unsafe_math_optimizations"
@@ -2431,7 +2431,7 @@
[(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
(unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand"
"w")
(match_operand:VCVTF 2 "s_register_operand"
"w")]
- NEON_VACMP))]
+ NEON_VAGLTE))]
"TARGET_NEON"
"vac<cmp_op_unsp>.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "type" "neon_fp_compare_s<q>")]
diff --git a/gcc/testsuite/gcc.target/arm/simd/pr97906.c
b/gcc/testsuite/gcc.target/arm/simd/pr97906.c
new file mode 100644
index 00000000000..7c972e311ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/pr97906.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x2_t f1(float32x2_t a, float32x2_t b)
+{
+ return vabs_f32 (a) >= vabs_f32 (b);
+}
+
+/* { dg-final { scan-assembler-times {\tvacle.f32\td[0-9]+, d[0-9]+, d[0-9]+}
1 } } */
+/* { dg-final { scan-assembler-not "vabs" } } */
