On Wed, May 26, 2021 at 03:24:00PM +0200, Jan-Benedict Glaw wrote:
> thanks, committed with above changes.
This patch removes useless register keywords from several backends and one
spot in the Ada FE.
Committed to trunk as obvious.
2021-05-26 Jakub Jelinek <ja...@redhat.com>
gcc/
* config/epiphany/epiphany.c (epiphany_print_operand_address): Remove
register keywords.
* config/microblaze/microblaze.c (microblaze_legitimize_address,
call_internal1,
microblaze_option_override, print_operand): Likewise.
* config/microblaze/microblaze.md (call_internal_plt,
call_value_intern_plt, call_value_intern): Likewise.
* config/arm/aout.h (ASM_OUTPUT_ALIGN): Likewise.
* config/iq2000/iq2000.md (call_internal1, call_value_internal1,
call_value_multiple_internal1): Likewise.
* config/bfin/bfin.c (symbolic_reference_mentioned_p): Likewise.
gcc/ada/
* init.c (__gnat_error_handler): Remove register keyword.
--- gcc/config/epiphany/epiphany.c.jj 2021-01-04 10:25:41.986198122 +0100
+++ gcc/config/epiphany/epiphany.c 2021-05-26 15:28:55.058022984 +0200
@@ -1394,7 +1394,7 @@ epiphany_print_operand (FILE *file, rtx
static void
epiphany_print_operand_address (FILE *file, machine_mode /*mode*/, rtx addr)
{
- register rtx base, index = 0;
+ rtx base, index = 0;
int offset = 0;
switch (GET_CODE (addr))
--- gcc/config/microblaze/microblaze.c.jj 2021-01-04 10:25:43.390182224
+0100
+++ gcc/config/microblaze/microblaze.c 2021-05-26 15:30:50.775400178 +0200
@@ -991,7 +991,7 @@ static rtx
microblaze_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
machine_mode mode ATTRIBUTE_UNUSED)
{
- register rtx xinsn = x, result;
+ rtx xinsn = x, result;
if (GET_CODE (xinsn) == CONST
&& flag_pic && pic_address_needs_scratch (xinsn))
@@ -1011,10 +1011,10 @@ microblaze_legitimize_address (rtx x, rt
if (GET_CODE (xinsn) == PLUS)
{
- register rtx xplus0 = XEXP (xinsn, 0);
- register rtx xplus1 = XEXP (xinsn, 1);
- register enum rtx_code code0 = GET_CODE (xplus0);
- register enum rtx_code code1 = GET_CODE (xplus1);
+ rtx xplus0 = XEXP (xinsn, 0);
+ rtx xplus1 = XEXP (xinsn, 1);
+ enum rtx_code code0 = GET_CODE (xplus0);
+ enum rtx_code code1 = GET_CODE (xplus1);
if (code0 != REG && code1 == REG)
{
@@ -1736,9 +1736,9 @@ microblaze_version_to_int (const char *v
static void
microblaze_option_override (void)
{
- register int i, start;
- register int regno;
- register machine_mode mode;
+ int i, start;
+ int regno;
+ machine_mode mode;
int ver;
microblaze_section_threshold = (global_options_set.x_g_switch_value
@@ -1891,11 +1891,11 @@ microblaze_option_override (void)
for (mode = VOIDmode;
mode != MAX_MACHINE_MODE; mode = (machine_mode) ((int) mode + 1))
{
- register int size = GET_MODE_SIZE (mode);
+ int size = GET_MODE_SIZE (mode);
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
- register int ok;
+ int ok;
if (mode == CCmode)
{
@@ -2267,7 +2267,7 @@ microblaze_initial_elimination_offset (i
void
print_operand (FILE * file, rtx op, int letter)
{
- register enum rtx_code code;
+ enum rtx_code code;
if (PRINT_OPERAND_PUNCT_VALID_P (letter))
{
@@ -2406,7 +2406,7 @@ print_operand (FILE * file, rtx op, int
else if (code == REG || code == SUBREG)
{
- register int regnum;
+ int regnum;
if (code == REG)
regnum = REGNO (op);
@@ -2431,7 +2431,7 @@ print_operand (FILE * file, rtx op, int
rtx mem_reg = XEXP (op, 0);
if (GET_CODE (mem_reg) == REG)
{
- register int regnum = REGNO (mem_reg);
+ int regnum = REGNO (mem_reg);
fprintf (file, "%s", reg_names[regnum]);
}
}
--- gcc/config/microblaze/microblaze.md.jj 2021-01-04 10:25:43.440181658
+0100
+++ gcc/config/microblaze/microblaze.md 2021-05-26 15:31:54.185510927 +0200
@@ -2107,8 +2107,8 @@ (define_insn "call_internal_plt"
(use (reg:SI R_GOT))]
"flag_pic"
{
- register rtx target2 = gen_rtx_REG (Pmode,
- GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ rtx target2
+ = gen_rtx_REG (Pmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
gen_rtx_CLOBBER (VOIDmode, target2);
return "brlid\tr15,%0\;%#";
}
@@ -2122,9 +2122,9 @@ (define_insn "call_internal1"
(clobber (reg:SI R_SR))]
""
{
- register rtx target = operands[0];
- register rtx target2 = gen_rtx_REG (Pmode,
- GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ rtx target = operands[0];
+ rtx target2
+ = gen_rtx_REG (Pmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
if (GET_CODE (target) == SYMBOL_REF) {
if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
gen_rtx_CLOBBER (VOIDmode, target2);
@@ -2216,7 +2216,8 @@ (define_insn "call_value_intern_plt"
(use (match_operand:SI 4 "register_operand"))]
"flag_pic"
{
- register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST +
MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ rtx target2
+ = gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
gen_rtx_CLOBBER (VOIDmode,target2);
return "brlid\tr15,%1\;%#";
@@ -2232,8 +2233,9 @@ (define_insn "call_value_intern"
(clobber (match_operand:SI 3 "register_operand" "=d"))]
""
{
- register rtx target = operands[1];
- register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST +
MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ rtx target = operands[1];
+ rtx target2
+ = gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
if (GET_CODE (target) == SYMBOL_REF)
{
--- gcc/config/arm/aout.h.jj 2021-01-04 10:25:44.369171138 +0100
+++ gcc/config/arm/aout.h 2021-05-26 15:27:34.829148099 +0200
@@ -257,7 +257,7 @@
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
do \
{ \
- register int amount = 1 << (POWER); \
+ int amount = 1 << (POWER); \
\
if (amount == 2) \
fprintf (STREAM, "\t.even\n"); \
--- gcc/config/iq2000/iq2000.md.jj 2021-01-04 10:25:45.760155388 +0100
+++ gcc/config/iq2000/iq2000.md 2021-05-26 15:29:28.407555295 +0200
@@ -1553,7 +1553,7 @@ (define_insn "call_internal1"
""
"*
{
- register rtx target = operands[0];
+ rtx target = operands[0];
if (GET_CODE (target) == CONST_INT)
return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
@@ -1641,7 +1641,7 @@ (define_insn "call_value_internal1"
""
"*
{
- register rtx target = operands[1];
+ rtx target = operands[1];
if (GET_CODE (target) == CONST_INT)
return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
@@ -1678,7 +1678,7 @@ (define_insn "call_value_multiple_intern
""
"*
{
- register rtx target = operands[1];
+ rtx target = operands[1];
if (GET_CODE (target) == CONST_INT)
return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
--- gcc/config/bfin/bfin.c.jj 2021-01-04 10:25:46.735144347 +0100
+++ gcc/config/bfin/bfin.c 2021-05-26 15:28:21.195497867 +0200
@@ -1773,8 +1773,8 @@ function_arg_regno_p (int n)
int
symbolic_reference_mentioned_p (rtx op)
{
- register const char *fmt;
- register int i;
+ const char *fmt;
+ int i;
if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
return 1;
@@ -1784,7 +1784,7 @@ symbolic_reference_mentioned_p (rtx op)
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (op, i) - 1; j >= 0; j--)
if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
--- gcc/ada/init.c.jj 2021-05-07 17:34:07.123772880 +0200
+++ gcc/ada/init.c 2021-05-26 15:33:04.170529466 +0200
@@ -1989,7 +1989,7 @@ __gnat_error_handler (int sig, siginfo_t
anything else.
This mechanism is only need in kernel mode. */
#if !(defined (__RTP__) || defined (VTHREADS)) && ((CPU == PPCE500V2) || (CPU
== PPC85XX))
- register unsigned msr;
+ unsigned msr;
/* Read the MSR value */
asm volatile ("mfmsr %0" : "=r" (msr));
/* Force the SPE bit if not set. */
Jakub
