Jonathan Wright <jonathan.wri...@arm.com> writes:
> Hi,
>
> As subject, this patch implements v[r]addhn2 and v[r]subhn2 Neon intrinsic
> RTL patterns using a vec_concat of a register_operand and an ADDSUBHN
> unspec - instead of just an ADDSUBHN2 unspec. This more relaxed pattern
> allows for more aggressive combinations and ultimately better code
> generation - which will be confirmed by a new set of tests in
> gcc.target/aarch64/narrow_high_combine.c (patch 5/5 in this series).
>
> This patch also removes the now redundant [R]ADDHN2 and [R]SUBHN2
> unspecs and their iterator.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issues.
>
> Ok for master?
OK, thanks.
Richard
> Thanks,
> Jonathan
>
> ---
>
> gcc/ChangeLog:
>
> 2021-03-03 Jonathan Wright <jonathan.wri...@arm.com>
>
> * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>):
> Implement as an expand emitting a big/little endian
> instruction pattern.
> (aarch64_<sur><addsub>hn2<mode>_insn_le): Define.
> (aarch64_<sur><addsub>hn2<mode>_insn_be): Define.
> * config/aarch64/iterators.md: Remove UNSPEC_[R]ADDHN2 and
> UNSPEC_[R]SUBHN2 unspecs and ADDSUBHN2 iterator.
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index
> 99620895e7874cdfe346eb8994fa7b519c650f88..69d48fea16b732c20db0ee400782ef9b73982c47
> 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -4594,17 +4594,48 @@
> [(set_attr "type" "neon_<addsub>_halve_narrow_q")]
> )
>
> -(define_insn "aarch64_<sur><addsub>hn2<mode>"
> +(define_insn "aarch64_<sur><addsub>hn2<mode>_insn_le"
> [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> - (unspec:<VNARROWQ2> [(match_operand:<VNARROWQ> 1 "register_operand"
> "0")
> - (match_operand:VQN 2 "register_operand" "w")
> - (match_operand:VQN 3 "register_operand" "w")]
> - ADDSUBHN2))]
> - "TARGET_SIMD"
> + (vec_concat:<VNARROWQ2>
> + (match_operand:<VNARROWQ> 1 "register_operand" "0")
> + (unspec:<VNARROWQ> [(match_operand:VQN 2 "register_operand" "w")
> + (match_operand:VQN 3 "register_operand" "w")]
> + ADDSUBHN)))]
> + "TARGET_SIMD && !BYTES_BIG_ENDIAN"
> + "<sur><addsub>hn2\\t%0.<V2ntype>, %2.<Vtype>, %3.<Vtype>"
> + [(set_attr "type" "neon_<addsub>_halve_narrow_q")]
> +)
> +
> +(define_insn "aarch64_<sur><addsub>hn2<mode>_insn_be"
> + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> + (vec_concat:<VNARROWQ2>
> + (unspec:<VNARROWQ> [(match_operand:VQN 2 "register_operand" "w")
> + (match_operand:VQN 3 "register_operand" "w")]
> + ADDSUBHN)
> + (match_operand:<VNARROWQ> 1 "register_operand" "0")))]
> + "TARGET_SIMD && BYTES_BIG_ENDIAN"
> "<sur><addsub>hn2\\t%0.<V2ntype>, %2.<Vtype>, %3.<Vtype>"
> [(set_attr "type" "neon_<addsub>_halve_narrow_q")]
> )
>
> +(define_expand "aarch64_<sur><addsub>hn2<mode>"
> + [(match_operand:<VNARROWQ2> 0 "register_operand")
> + (match_operand:<VNARROWQ> 1 "register_operand")
> + (unspec [(match_operand:VQN 2 "register_operand")
> + (match_operand:VQN 3 "register_operand")]
> + ADDSUBHN)]
> + "TARGET_SIMD"
> + {
> + if (BYTES_BIG_ENDIAN)
> + emit_insn (gen_aarch64_<sur><addsub>hn2<mode>_insn_be (operands[0],
> + operands[1], operands[2], operands[3]));
> + else
> + emit_insn (gen_aarch64_<sur><addsub>hn2<mode>_insn_le (operands[0],
> + operands[1], operands[2], operands[3]));
> + DONE;
> + }
> +)
> +
> ;; pmul.
>
> (define_insn "aarch64_pmul<mode>"
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index
> 69d9dbebe8f1fcee39e93586b97da1a887fd94e3..d13f54a32465619110d7d014fdfe8aaf22384189
> 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -514,10 +514,6 @@
> UNSPEC_RADDHN ; Used in aarch64-simd.md.
> UNSPEC_SUBHN ; Used in aarch64-simd.md.
> UNSPEC_RSUBHN ; Used in aarch64-simd.md.
> - UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
> - UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
> - UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
> - UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
> UNSPEC_SQDMULH ; Used in aarch64-simd.md.
> UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
> UNSPEC_PMUL ; Used in aarch64-simd.md.
> @@ -2241,9 +2237,6 @@
> (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
> UNSPEC_SUBHN UNSPEC_RSUBHN])
>
> -(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
> - UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
> -
> (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
> UNSPEC_FMAXNM UNSPEC_FMINNM])
>
> @@ -2996,8 +2989,6 @@
> (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
> (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
> (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
> - (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
> - (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
> (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
> (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
> (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
> @@ -3060,11 +3051,7 @@
> (UNSPEC_ADDHN "add")
> (UNSPEC_SUBHN "sub")
> (UNSPEC_RADDHN "add")
> - (UNSPEC_RSUBHN "sub")
> - (UNSPEC_ADDHN2 "add")
> - (UNSPEC_SUBHN2 "sub")
> - (UNSPEC_RADDHN2 "add")
> - (UNSPEC_RSUBHN2 "sub")])
> + (UNSPEC_RSUBHN "sub")])
>
> ;; BSL variants: first commutative operand.
> (define_int_attr bsl_1st [(1 "w") (2 "0")])
