Hi, The existing vec_pack_trunc RTL pattern emits an opaque two- instruction assembly code sequence that prevents proper instruction scheduling. This commit changes the pattern to an expander that emits individual xtn and xtn2 instructions.
This commit also consolidates the duplicate truncation patterns.
Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-05-17 Jonathan Wright <jonathan.wri...@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_pack_trunc_<mode>):
Remove as duplicate of...
(aarch64_xtn<mode>): This.
(aarch64_xtn2<mode>_le): Move position in file.
(aarch64_xtn2<mode>_be): Move position in file.
(aarch64_xtn2<mode>): Move position in file.
(vec_pack_trunc_<mode>): Define as an expander.
rb14480.patch
Description: rb14480.patch
