On Tue, Feb 7, 2012 at 11:00 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
>>> Hmm. Well, the only thing that's going to work for x86 is the >>> double-compare >>> elimination portion. >>> >>> If we want to use this pass for x86, then for 4.8 we should also fix the >>> discrepancy between the compare-elim canonical >>> >>> [(operate) >>> (set-cc)] >>> >>> and the combine canonical >>> >>> [(set-cc) >>> (operate)] >>> >>> (Because of the simplicity of the substitution in compare-elim, I prefer >>> the former as the canonical canonical.) >> >> You are probably referring to following testcase: >> >> --cut here-- >> int test (int a, int b) >> { >> int lt = a + b < 0; >> int eq = a + b == 0; >> if (lt) >> return 1; >> return eq; >> } >> --cut here-- >> >> where combine creates: >> >> Trying 8 -> 9: >> Successfully matched this instruction: >> (parallel [ >> (set (reg:CCZ 17 flags) >> (compare:CCZ (plus:SI (reg/v:SI 63 [ a ]) >> (reg/v:SI 64 [ b ])) >> (const_int 0 [0]))) >> (set (reg:SI 60 [ D.1710 ]) >> (plus:SI (reg/v:SI 63 [ a ]) >> (reg/v:SI 64 [ b ]))) >> ]) > > Attached patch teaches combine to swap operands of a double set > pattern and retries recognition. Also added are minimum > target-dependant changes to handle the testcase above. Please ignore this idea. I am preparing target-only patchset that moves x86 entirely to post-reload flags handling (similar to rx and mn10300 targets). Not a 4.7 material in any way. Uros.