Hi!
On Fri, May 07, 2021 at 10:53:31AM -0500, Pat Haugen wrote:
> Code that has heavy register pressure on Altivec registers can suffer from
> over-aggressive scheduling during sched1, which then leads to increased
> register spill. This is due to the fact that registers that prefer
> ALTIVEC_REGS are currently assigned an allocno class of VSX_REGS. This then
> misleads the scheduler to think there are 64 regs available, when in reality
> there are only 32 Altivec regs. This patch fixes the problem by assigning an
> allocno class of ALTIVEC_REGS and adding ALTIVEC_REGS as a pressure class.
> gcc/testsuite/ChangeLog:
>
> * gcc.target/powerpc/fold-vec-insert-float-p9.c: Adjust instruction
> counts.
(line too long)
> + case VSX_REGS:
> + if (best_class == ALTIVEC_REGS)
> + return ALTIVEC_REGS;
Should this be under just this case, or should we do this always?
Maybe change the big switch to be on best_class instead of on
allocno_class?
> --- a/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vec-rlmi-rlnm.c
> @@ -62,6 +62,6 @@ rlnm_test_2 (vector unsigned long long x, vector unsigned
> long long y,
> /* { dg-final { scan-assembler-times "vextsb2d" 1 } } */
> /* { dg-final { scan-assembler-times "vslw" 1 } } */
> /* { dg-final { scan-assembler-times "vsld" 1 } } */
> -/* { dg-final { scan-assembler-times "xxlor" 3 } } */
> +/* { dg-final { scan-assembler-times "xxlor" 2 } } */
> /* { dg-final { scan-assembler-times "vrlwnm" 2 } } */
> /* { dg-final { scan-assembler-times "vrldnm" 2 } } */
So what is this replaced with? Was it an "xxlmr" and it is just
unnecessary now?
The patch is okay for trunk. Thanks!
Segher
