Re: [PATCH 13/20] aarch64: Use RTL builtins for FP ml[as][q]_laneq intrinsics

[Jonathan Wright via Gcc-patches]

Hi Richard,

I think you may be referencing an older checkout as we refactored this
pattern in a previous change to:

(define_insn "mul_lane<mode>3"
 [(set (match_operand:VMUL 0 "register_operand" "=w")
       (mult:VMUL
   (vec_duplicate:VMUL
     (vec_select:<VEL>
       (match_operand:VMUL 2 "register_operand" "<h_con>")
       (parallel [(match_operand:SI 3 "immediate_operand" "i")])))
   (match_operand:VMUL 1 "register_operand" "w")))]
  "TARGET_SIMD"
  {
    operands[3] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[3]));
    return "<f>mul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]";
  }
  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
)

which doesn't help us with the 'laneq' intrinsics as the machine mode for
operands 0 and 1 (of the laneq intrinsics) is narrower than the machine
mode for operand 2.

Thanks,
Jonathan
​
________________________________
From: Richard Sandiford <rdsandif...@googlemail.com>
Sent: 30 April 2021 19:18
To: Jonathan Wright <jonathan.wri...@arm.com>
Cc: gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 13/20] aarch64: Use RTL builtins for FP ml[as][q]_laneq 
intrinsics

Richard Sandiford via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> Jonathan Wright <jonathan.wri...@arm.com> writes:
>> diff --git a/gcc/config/aarch64/aarch64-simd.md 
>> b/gcc/config/aarch64/aarch64-simd.md
>> index 
>> bdee49f74f4725409d33af733bb55be290b3f0e7..234762960bd6df057394f753072ef65a6628a43d
>>  100644
>> --- a/gcc/config/aarch64/aarch64-simd.md
>> +++ b/gcc/config/aarch64/aarch64-simd.md
>> @@ -734,6 +734,22 @@
>>    [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
>>  )
>>
>> +(define_insn "mul_laneq<mode>3"
>> +  [(set (match_operand:VDQSF 0 "register_operand" "=w")
>> +    (mult:VDQSF
>> +      (vec_duplicate:VDQSF
>> +        (vec_select:<VEL>
>> +          (match_operand:V4SF 2 "register_operand" "w")
>> +          (parallel [(match_operand:SI 3 "immediate_operand" "i")])))
>> +      (match_operand:VDQSF 1 "register_operand" "w")))]
>> +  "TARGET_SIMD"
>> +  {
>> +    operands[3] = aarch64_endian_lane_rtx (V4SFmode, INTVAL (operands[3]));
>> +    return "fmul\\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[%3]";
>> +  }
>> +  [(set_attr "type" "neon_fp_mul_s_scalar<q>")]
>> +)
>> +

Oops, sorry, I just realised that this pattern does already exist as:

(define_insn "*aarch64_mul3_elt<mode>"
 [(set (match_operand:VMUL 0 "register_operand" "=w")
    (mult:VMUL
      (vec_duplicate:VMUL
          (vec_select:<VEL>
            (match_operand:VMUL 1 "register_operand" "<h_con>")
            (parallel [(match_operand:SI 2 "immediate_operand")])))
      (match_operand:VMUL 3 "register_operand" "w")))]
  "TARGET_SIMD"
  {
    operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
    return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
  }
  [(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
)

Thanks,
Richard