Hi,

As subject, this patch rewrites the vq[r]dmulh[q]_n Neon intrinsics to use
RTL builtins rather than inline assembly code, allowing for better scheduling
and optimization.

Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-02-08  Jonathan Wright  <jonathan.wri...@arm.com>

        * config/aarch64/aarch64-simd-builtins.def: Add sq[r]dmulh_n
        builtin generator macros.
        * config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_n<mode>):
        Define.
        * config/aarch64/arm_neon.h (vqdmulh_n_s16): Use RTL builtin
        instead of inline asm.
        (vqdmulh_n_s32): Likewise.
        (vqdmulhq_n_s16): Likewise.
        (vqdmulhq_n_s32): Likewise.
        (vqrdmulh_n_s16): Likewise.
        (vqrdmulh_n_s32): Likewise.
        (vqrdmulhq_n_s16): Likewise.
        (vqrdmulhq_n_s32): Likewise.

Attachment: rb14130.patch
Description: rb14130.patch

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