Tamar Christina <tamar.christ...@arm.com> writes: > Hi Richard, > > The 04/16/2021 12:23, Richard Sandiford wrote: >> Tamar Christina <tamar.christ...@arm.com> writes: >> > diff --git a/gcc/config/aarch64/aarch64-sve.md >> > b/gcc/config/aarch64/aarch64-sve.md >> > index >> > 7db2938bb84e04d066a7b07574e5cf344a3a8fb6..2cdc6338902216760622a39b14f0076994458c98 >> > 100644 >> > --- a/gcc/config/aarch64/aarch64-sve.md >> > +++ b/gcc/config/aarch64/aarch64-sve.md >> > @@ -8657,6 +8657,22 @@ (define_insn "@aarch64_sve_<perm_insn><mode>" >> > "<perm_insn>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>" >> > ) >> > >> > +;; Special purpose permute used by the predicate generation instructions. >> > +;; This version only accepts VNx16BI as input but can output as any >> > predicate >> > +;; type and will reinterpet the input registers as the type in operand 3. >> >> I think it would be more accurate to say something like: >> >> ;; Special purpose permute used by the predicate generation instructions. >> ;; Unlike the normal permute patterns, these instructions operate on VNx16BI >> ;; regardless of the element size, so that all input and output bits are >> ;; well-defined. Operand 3 then indicates the size of the permute. >> >> > +(define_insn "@aarch64_sve_trn1_conv<mode>" >> > + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") >> > + (unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand" "Upa") >> > + (match_operand:VNx16BI 2 "register_operand" "Upa") >> > + (clobber >> > + (match_operand:PRED_ALL 3 "register_operand" "=Upa")) >> >> I don't think we need a register for operand 3. We could just use the >> CONST0_RTX of the mode: >> >> (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero") >> > > Ah! good shout! I was wondering if I could avoid the clobber and this works > great. > > Thanks! > > Bootstrapped and regtested on aarch64-none-linux-gnu and no issues. > > Ok for trunk and GCC 10?
OK, thanks. Richard
