On Fri, Apr 09, 2021 at 10:43:58AM -0400, Michael Meissner wrote:
>         (Fv mode attribute): Add KFmode and TFmode.
>         (mov<FPMASK:mode><FPMASK2:mode>cc_fpmask): Replace
>         mov<SFDF:mode><SFDF2:mode>cc_p9.  Add IEEE 128-bit fp support.
>         (mov<FPMASK:mode><FPMASK2:mode>cc_invert_fpmask): Replace
>         mov<SFDF:mode><SFDF2:mode>cc_invert_p9.  Add IEEE 128-bit fp
>         support.
>         (fpmask<mode>): Add IEEE 128-bit fp support.  Enable generator to
>         build te RTL.
>         (xxsel<mode>): Add IEEE 128-bit fp support.  Enable generator to
>         build te RTL.
> @@ -608,8 +621,13 @@ (define_mode_attr Ff             [(SF "f") (DF "d") (DI 
> "d")])
>  ; SF/DF constraint for arithmetic on VSX registers using instructions added 
> in
>  ; ISA 2.06 (power7).  This includes instructions that normally target DF 
> mode,
>  ; but are used on SFmode, since internally SFmode values are kept in the 
> DFmode
> -; format.
> -(define_mode_attr Fv         [(SF "wa") (DF "wa") (DI "wa")])
> +; format.  Also include IEEE 128-bit instructions which are restricted to the
> +; Altivec registers.
> +(define_mode_attr Fv         [(SF "wa")
> +                              (DF "wa")
> +                              (DI "wa")
> +                              (KF "v")
> +                              (TF "v")])

Eww.  Please just split the patterns.  Fv should just go away, it is
always "wa" currently.  Removing that cascades to more cleanups, which
is why I haven't done it yet, it takes time.

Almost all places that use Fv have no use at all for KF.

>  (define_expand "mov<mode>cc"
> -   [(set (match_operand:SFDF 0 "gpc_reg_operand")
> -      (if_then_else:SFDF (match_operand 1 "comparison_operator")
> -                         (match_operand:SFDF 2 "gpc_reg_operand")
> -                         (match_operand:SFDF 3 "gpc_reg_operand")))]
> +   [(set (match_operand:FPMASK 0 "gpc_reg_operand")
> +      (if_then_else:FPMASK (match_operand 1 "comparison_operator")
> +                           (match_operand:FPMASK 2 "gpc_reg_operand")
> +                           (match_operand:FPMASK 3 "gpc_reg_operand")))]

So you really want SFDFQF or such?  That is much more generic than
"FPMASK", which doesn't explain what it means at all, either.

But, you can keep the patterns separate as well.

> - [(set_attr "length" "8")
> + ;; length is 12 in case we need to add XXPERMDI
> + [(set_attr "length" "12")

Which is only for QP.  So really, just keep the patterns split.

> +  return (FLOAT128_IEEE_P (<MODE>mode)
> +       ? "xscmp%V1qp %0,%2,%3"
> +       : "xscmp%V1dp %x0,%x2,%x3");

Different output as well.

> -(define_insn "*xxsel<mode>"
> -  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
> -     (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" 
> "wa")
> -                            (match_operand:V2DI 2 "zero_constant" ""))
> -                        (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
> -                        (match_operand:SFDF 4 "vsx_register_operand" 
> "<Fv>")))]
> +(define_insn "xxsel<mode>"
> +  [(set (match_operand:FPMASK 0 "vsx_register_operand" "=wa")
> +     (if_then_else:FPMASK
> +      (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
> +          (match_operand:V2DI 2 "zero_constant" ""))
> +      (match_operand:FPMASK 3 "vsx_register_operand" "wa")
> +      (match_operand:FPMASK 4 "vsx_register_operand" "wa")))]
>    "TARGET_P9_MINMAX"
>    "xxsel %x0,%x4,%x3,%x1"
>    [(set_attr "type" "vecmove")])

Please keep that a "*"; it should be generated via "mov<mode>cc".

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
> @@ -0,0 +1,93 @@

> +/* { dg-final { scan-assembler     {\mxxsel\M}        } } */

> +/* { dg-final { scan-assembler-not {\mfsel\M}         } } */

It is somewhat problematic to require xxsel and disallow fsel (for one
thing, the compiler could always generated xxsel instead of any fsel).
But it will probably keep working fine, the routines here are very
short.

> +__float128
> +eq_f128_d (__float128 a, __float128 b, double x, double y)
> +{
> +  return (x != y) ? a : b;
> +}

So "==" here.


Segher

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