Joel Hutton <joel.hut...@arm.com> writes:
>>> gcc/testsuite/ChangeLog:
>>>
>>> PR target/99102
>>> * gcc.target/aarch64/sve/pr99102.c: New test.
>>
>>(The filename is out of date, but the git hook would catch that.)
> Fixed and committed.
>
>>
>>>
>>> diff --git a/gcc/testsuite/gcc.dg/vect/pr99102.c
>>> b/gcc/testsuite/gcc.dg/vect/pr99102.c
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..9d321b97a68c05ad08646e8e2d69
>>> 79c2030c65e6
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.dg/vect/pr99102.c
>>> @@ -0,0 +1,20 @@
>>> +/* { dg-options "-O2 -ftree-vectorize" } */
>>> +/* { dg-additional-options "-msve-vector-bits=256" { target
>>> +aarch64_sve } } */
>>
>>I should have realised this earlier, sorry, but I think we want this to be
>>conditional on aarch64_sve256_hw instead. Same for the scan-tree-dump below.
>>
>>When running the testsuite on SVE hardware, the above would force a VL of 256
>>even if the actual VL is different, so the test would fail at runtime for
>>128-bit SVE, 512-bit SVE, etc.
>>
>>Thanks,
>>Richard.
>>
>
> Patch attached to add this, Ok?
OK, thanks.
Richard
