[PATCH v2 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

[YunQiang Su]

It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32.
While the 32bit pair of <load>l <load>r is mark as SUBREG, so they are
not in SImode, make it fail to find suitable insn.

gcc/ChangeLog:

       * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
       If TARGET_64BIT and dest is SUBREG, we check the width, if it
       equal to SImode, we use SImode operation, just like what we are
       doing for REG one.
---
 gcc/ChangeLog          | 8 ++++++++
 gcc/config/mips/mips.c | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0b3bdcee619..3c91791feac 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2021-02-18  YunQiang Su  <yunqiang...@cipunited.com>
+
+       PR target/98996
+       * config/mips/mips.c (mips_expand_ext_as_unaligned_load):
+       If TARGET_64BIT and dest is SUBREG, we check the width, if it
+       equal to SImode, we use SImode operation, just like what we are
+       doing for REG one.
+
 2021-02-17  Julian Brown  <jul...@codesourcery.com>
 
        * gimplify.c (gimplify_scan_omp_clauses): Handle ATTACH_DETACH
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8bd2d29552e..e901d860c3d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8400,7 +8400,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, 
HOST_WIDE_INT width,
   /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
      be a DImode, create a new temp and emit a zero extend at the end.  */
   if (GET_MODE (dest) == DImode
-      && REG_P (dest)
+      && (REG_P (dest) || (SUBREG_P(dest) && !MEM_P(SUBREG_REG(dest))))
       && GET_MODE_BITSIZE (SImode) == width)
     {
       dest1 = dest;
-- 
2.20.1