Hi Victor, Thanks for the patch. I have a couple of very minor comments below, but otherwise it looks good to go. However, it will need to wait for stage 1 to open, unless it fixes a regression.
Victor Do Nascimento via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > diff --git a/gcc/config/aarch64/aarch64-simd.md > b/gcc/config/aarch64/aarch64-simd.md > index 68baf416045..4623cbb95f4 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -205,6 +205,16 @@ > [(set_attr "type" "neon_stp")] > ) > > +(define_insn "aarch64_simd_stp<mode>" > + [(set (match_operand:VP_2E 0 "aarch64_mem_pair_operand" "=Ump,Ump") > + (vec_duplicate:VP_2E (match_operand:<VEL> 1 "register_operand" > "w,r")))] > + "TARGET_SIMD" > + "@ > + stp\\t%<Vetype>1, %<Vetype>1, %z0 > + stp\\t%<vw>1, %<vw>1, %z0" > + [(set_attr "type" "neon_stp<q>, store_<ldpstp_vel_sz>")] Minor formatting nit, but: these patterns are generally indented by 2 spaces rather than 4 (at least in config/aarch64). Also, it would be good if the (vec_duplicate:…) lined up with the (match_operand:…) I think the type for the first alternative should be neon_stp rather than neon_stp<q>. The instruction only ever stores S or D registers, whereas neon_stp_q is for storing Q registers. Thanks, Richard
