Hi,
As subject, this patch adds tests for vpaddq_* Neon intrinsics. Since these
intrinsics are only supported for AArch64, these tests are restricted to
only run on AArch64 targets.
(There are currently no tests covering these intrinsics.)
Ok for master?
Thanks,
Jonathan
---
gcc/testsuite/ChangeLog:
2021-02-09 Jonathan Wright <jonathan.wri...@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vpXXXq.inc:
New test template.
* gcc.target/aarch64/advsimd-intrinsics/vpaddq.c: New test.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXXq.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXXq.inc
new file mode 100644
index 0000000000000000000000000000000000000000..3c27d32992c0e3a1d69580d1699c28f01fbb76ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXXq.inc
@@ -0,0 +1,96 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPXXXQ1(INSN, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector, T1, W, N)); \
+ vst1q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VPXXXQ(INSN, T1, T2, W, N) \
+ TEST_VPXXXQ1(INSN, T1, T2, W, N) \
+
+ DECL_VARIABLE(vector, int, 8, 16);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 8, 16);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+ DECL_VARIABLE(vector, float, 16, 8);
+#endif
+ DECL_VARIABLE(vector, float, 32, 4);
+ DECL_VARIABLE(vector, float, 64, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 16);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 16);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+ DECL_VARIABLE(vector_res, float, 16, 8);
+#endif
+ DECL_VARIABLE(vector_res, float, 32, 4);
+ DECL_VARIABLE(vector_res, float, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, q, int, s, 8, 16);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 8, 16);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+ VLOAD(vector, buffer, q, float, f, 16, 8);
+#endif
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+ VLOAD(vector, buffer, q, float, f, 64, 2);
+
+ /* Apply a binary operator named INSN_NAME. */
+ TEST_VPXXXQ(INSN_NAME, int, s, 8, 16);
+ TEST_VPXXXQ(INSN_NAME, int, s, 16, 8);
+ TEST_VPXXXQ(INSN_NAME, int, s, 32, 4);
+ TEST_VPXXXQ(INSN_NAME, int, s, 64, 2);
+ TEST_VPXXXQ(INSN_NAME, uint, u, 8, 16);
+ TEST_VPXXXQ(INSN_NAME, uint, u, 16, 8);
+ TEST_VPXXXQ(INSN_NAME, uint, u, 32, 4);
+ TEST_VPXXXQ(INSN_NAME, uint, u, 64, 2);
+#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+ TEST_VPXXXQ(INSN_NAME, float, f, 16, 8);
+#endif
+ TEST_VPXXXQ(INSN_NAME, float, f, 32, 4);
+ TEST_VPXXXQ(INSN_NAME, float, f, 64, 2);
+
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+ CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, "");
+#endif
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddq.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddq.c
new file mode 100644
index 0000000000000000000000000000000000000000..f15ada8aa52ae004389e014e4c45a5ebdddab291
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddq.c
@@ -0,0 +1,40 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vpaddq
+#define TEST_MSG "VPADDQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 8, 16) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xf1, 0xf5, 0xf9, 0xfd,
+ 0xe1, 0xe5, 0xe9, 0xed,
+ 0xf1, 0xf5, 0xf9, 0xfd };
+VECT_VAR_DECL(expected, int, 16, 8) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed,
+ 0xffe1, 0xffe5, 0xffe9, 0xffed };
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0xffffffe1, 0xffffffe5,
+ 0xffffffe1, 0xffffffe5 };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xffffffffffffffe1,
+ 0xffffffffffffffe1 };
+VECT_VAR_DECL(expected, uint, 8, 16) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xf1, 0xf5, 0xf9, 0xfd,
+ 0xe1, 0xe5, 0xe9, 0xed,
+ 0xf1, 0xf5, 0xf9, 0xfd };
+VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed,
+ 0xffe1, 0xffe5, 0xffe9, 0xffed };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffffffe1, 0xffffffe5,
+ 0xffffffe1, 0xffffffe5};
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffffffffffe1,
+ 0xffffffffffffffe1 };
+#if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcfc0, 0xcec0, 0xcdc0, 0xccc0,
+ 0xcfc0, 0xcec0, 0xcdc0, 0xccc0 };
+#endif
+VECT_VAR_DECL(expected, hfloat, 32, 4) [] = { 0xc1f80000, 0xc1d80000,
+ 0xc1f80000, 0xc1d80000 };
+VECT_VAR_DECL(expected, hfloat, 64, 2) [] = { 0xc03f000000000000,
+ 0xc03f000000000000 };
+
+#include "vpXXXq.inc"
