Hi,
As subject, this patch adds tests for vmlal_high_* and vmlsl_high_*
Neon intrinsics. Since these intrinsics are only supported for AArch64,
these tests are restricted to only run on AArch64 targets.
Ok for master?
Thanks,
Jonathan
---
gcc/testsuite/ChangeLog:
2021-01-31 Jonathan Wright <jonathan.wri...@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_high.inc:
New test template.
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_lane.inc:
New test template.
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_laneq.inc:
New test template.
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_n.inc:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_high.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_high_lane.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_high_laneq.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_high_n.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_high.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_lane.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_laneq.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_n.c:
New test.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high.inc
new file mode 100644
index 0000000000000000000000000000000000000000..7c9ee26b142669c48d27aca6bd11988e948cf52d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high.inc
@@ -0,0 +1,89 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = OP(vector, vector3, vector4),
+ then store the result. */
+#define TEST_VMLXL_HIGH1(INSN, T1, T2, W1, W2, N1, N2) \
+ VECT_VAR(vector_res, T1, W1, N1) = \
+ INSN##_##T2##W2(VECT_VAR(vector, T1, W1, N1), \
+ VECT_VAR(vector3, T1, W2, N2), \
+ VECT_VAR(vector4, T1, W2, N2)); \
+ vst1q_##T2##W1(VECT_VAR(result, T1, W1, N1), VECT_VAR(vector_res, T1, W1, N1))
+
+#define TEST_VMLXL_HIGH(INSN, T1, T2, W1, W2, N1, N2) \
+ TEST_VMLXL_HIGH1(INSN, T1, T2, W1, W2, N1, N2)
+
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector3, int, 8, 16);
+ DECL_VARIABLE(vector4, int, 8, 16);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 8);
+ DECL_VARIABLE(vector4, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 4);
+ DECL_VARIABLE(vector4, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector3, uint, 8, 16);
+ DECL_VARIABLE(vector4, uint, 8, 16);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector3, uint, 16, 8);
+ DECL_VARIABLE(vector4, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector3, uint, 32, 4);
+ DECL_VARIABLE(vector4, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector3, q, int, s, 8, 16, 0x55);
+ VDUP(vector4, q, int, s, 8, 16, 0xBB);
+ VDUP(vector3, q, int, s, 16, 8, 0x55);
+ VDUP(vector4, q, int, s, 16, 8, 0xBB);
+ VDUP(vector3, q, int, s, 32, 4, 0x55);
+ VDUP(vector4, q, int, s, 32, 4, 0xBB);
+ VDUP(vector3, q, uint, u, 8, 16, 0x55);
+ VDUP(vector4, q, uint, u, 8, 16, 0xBB);
+ VDUP(vector3, q, uint, u, 16, 8, 0x55);
+ VDUP(vector4, q, uint, u, 16, 8, 0xBB);
+ VDUP(vector3, q, uint, u, 32, 4, 0x55);
+ VDUP(vector4, q, uint, u, 32, 4, 0xBB);
+
+ TEST_VMLXL_HIGH(INSN_NAME, int, s, 16, 8, 8, 16);
+ TEST_VMLXL_HIGH(INSN_NAME, int, s, 32, 16, 4, 8);
+ TEST_VMLXL_HIGH(INSN_NAME, int, s, 64, 32, 2, 4);
+ TEST_VMLXL_HIGH(INSN_NAME, uint, u, 16, 8, 8, 16);
+ TEST_VMLXL_HIGH(INSN_NAME, uint, u, 32, 16, 4, 8);
+ TEST_VMLXL_HIGH(INSN_NAME, uint, u, 64, 32, 2, 4);
+
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_lane.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_lane.inc
new file mode 100644
index 0000000000000000000000000000000000000000..b5728550cc5d04817cf3ec28a19094aeca6ccf4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_lane.inc
@@ -0,0 +1,71 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vmlxl_high_lane(vector, vector3, vector4, lane),
+ then store the result. */
+#define TEST_VMLXL_HIGH_LANE1(INSN, T1, T2, W1, W2, N1, N2, V) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##_##T2##W1(VECT_VAR(vector, T1, W2, N2), \
+ VECT_VAR(vector3, T1, W1, N1), \
+ VECT_VAR(vector4, T1, W1, N2), \
+ V); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VMLXL_HIGH_LANE(INSN, T1, T2, W1, W2, N1, N2, V) \
+ TEST_VMLXL_HIGH_LANE1(INSN, T1, T2, W1, W2, N1, N2, V)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 8);
+ DECL_VARIABLE(vector4, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 4);
+ DECL_VARIABLE(vector4, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector3, uint, 16, 8);
+ DECL_VARIABLE(vector4, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector3, uint, 32, 4);
+ DECL_VARIABLE(vector4, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector3, q, int, s, 16, 8, 0x55);
+ VDUP(vector4, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, q, int, s, 32, 4, 0x55);
+ VDUP(vector4, , int, s, 32, 2, 0xBB);
+ VDUP(vector3, q, uint, u, 16, 8, 0x55);
+ VDUP(vector4, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, q, uint, u, 32, 4, 0x55);
+ VDUP(vector4, , uint, u, 32, 2, 0xBB);
+
+ TEST_VMLXL_HIGH_LANE(INSN_NAME, int, s, 16, 32, 8, 4, 2);
+ TEST_VMLXL_HIGH_LANE(INSN_NAME, int, s, 32, 64, 4, 2, 1);
+ TEST_VMLXL_HIGH_LANE(INSN_NAME, uint, u, 16, 32, 8, 4, 2);
+ TEST_VMLXL_HIGH_LANE(INSN_NAME, uint, u, 32, 64, 4, 2, 1);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_laneq.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_laneq.inc
new file mode 100644
index 0000000000000000000000000000000000000000..d970e19fd76f96cce916f699ca19a4fee9a8d026
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_laneq.inc
@@ -0,0 +1,71 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vmlxl_high_laneq(vector, vector3, vector4, lane),
+ then store the result. */
+#define TEST_VMLXL_HIGH_LANEQ1(INSN, T1, T2, W1, W2, N1, N2, V) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##_##T2##W1(VECT_VAR(vector, T1, W2, N2), \
+ VECT_VAR(vector3, T1, W1, N1), \
+ VECT_VAR(vector4, T1, W1, N1), \
+ V); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VMLXL_HIGH_LANEQ(INSN, T1, T2, W1, W2, N1, N2, V) \
+ TEST_VMLXL_HIGH_LANEQ1(INSN, T1, T2, W1, W2, N1, N2, V)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 8);
+ DECL_VARIABLE(vector4, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 4);
+ DECL_VARIABLE(vector4, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector3, uint, 16, 8);
+ DECL_VARIABLE(vector4, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector3, uint, 32, 4);
+ DECL_VARIABLE(vector4, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector3, q, int, s, 16, 8, 0x55);
+ VDUP(vector4, q, int, s, 16, 8, 0xBB);
+ VDUP(vector3, q, int, s, 32, 4, 0x55);
+ VDUP(vector4, q, int, s, 32, 4, 0xBB);
+ VDUP(vector3, q, uint, u, 16, 8, 0x55);
+ VDUP(vector4, q, uint, u, 16, 8, 0xBB);
+ VDUP(vector3, q, uint, u, 32, 4, 0x55);
+ VDUP(vector4, q, uint, u, 32, 4, 0xBB);
+
+ TEST_VMLXL_HIGH_LANEQ(INSN_NAME, int, s, 16, 32, 8, 4, 5);
+ TEST_VMLXL_HIGH_LANEQ(INSN_NAME, int, s, 32, 64, 4, 2, 3);
+ TEST_VMLXL_HIGH_LANEQ(INSN_NAME, uint, u, 16, 32, 8, 4, 7);
+ TEST_VMLXL_HIGH_LANEQ(INSN_NAME, uint, u, 32, 64, 4, 2, 1);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_n.inc
new file mode 100644
index 0000000000000000000000000000000000000000..65b278f137c54cb8d8dce84ebf219af8f4c0dee6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_n.inc
@@ -0,0 +1,62 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vmlxl_high_n(vector, vector2, val), then store the result. */
+#define TEST_VMLXL_HIGH_N1(INSN, T1, T2, W1, W2, N1, N2, V) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##_##T2##W1(VECT_VAR(vector, T1, W2, N2), \
+ VECT_VAR(vector2, T1, W1, N1), \
+ V); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VMLXL_HIGH_N(INSN, T1, T2, W1, W2, N1, N2, V) \
+ TEST_VMLXL_HIGH_N1(INSN, T1, T2, W1, W2, N1, N2, V)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector2, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector2, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector2, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector2, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector2, q, int, s, 16, 8, 0x55);
+ VDUP(vector2, q, int, s, 32, 4, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x55);
+ VDUP(vector2, q, uint, u, 32, 4, 0x55);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMLXL_HIGH_N(INSN_NAME, int, s, 16, 32, 8, 4, 0x11);
+ TEST_VMLXL_HIGH_N(INSN_NAME, int, s, 32, 64, 4, 2, 0x22);
+ TEST_VMLXL_HIGH_N(INSN_NAME, uint, u, 16, 32, 8, 4, 0x33);
+ TEST_VMLXL_HIGH_N(INSN_NAME, uint, u, 32, 64, 4, 2, 0x33);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high.c
new file mode 100644
index 0000000000000000000000000000000000000000..7fce05bff41c3919b06e5eff91bf37be55372a89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high.c
@@ -0,0 +1,20 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal_high
+#define TEST_MSG "VMLAL_HIGH"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 16, 8) [] = { 0xe907, 0xe908, 0xe909, 0xe90a,
+ 0xe90b, 0xe90c, 0xe90d, 0xe90e };
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x3e07, 0x3e08 };
+
+#include "vmlXl_high.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_lane.c
new file mode 100644
index 0000000000000000000000000000000000000000..1c904e2d3c8044053df1a2c75253a89a3afb98f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_lane.c
@@ -0,0 +1,16 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal_high_lane
+#define TEST_MSG "VMLAL_HIGH_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x3e07, 0x3e08 };
+
+#include "vmlXl_high_lane.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_laneq.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_laneq.c
new file mode 100644
index 0000000000000000000000000000000000000000..b885e75eb149df2c0f1ad3f4d33136da3d625a42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_laneq.c
@@ -0,0 +1,16 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal_high_laneq
+#define TEST_MSG "VMLAL_HIGH_LANEQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x3e07, 0x3e08 };
+
+#include "vmlXl_high_laneq.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_n.c
new file mode 100644
index 0000000000000000000000000000000000000000..68dda03862fd6ed9e4a1fd9c6d9a288023a847e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_n.c
@@ -0,0 +1,16 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal_high_n
+#define TEST_MSG "VMLAL_HIGH_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0x595, 0x596, 0x597, 0x598 };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xb3a, 0xb3b };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0x10df, 0x10e0 };
+
+#include "vmlXl_high_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high.c
new file mode 100644
index 0000000000000000000000000000000000000000..169b84227ea2e13aaf89bba8f6cd452a81649ac4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high.c
@@ -0,0 +1,24 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl_high
+#define TEST_MSG "VMLSL_HIGH"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 16, 8) [] = { 0x16d9, 0x16da, 0x16db, 0x16dc,
+ 0x16dd, 0x16de, 0x16df, 0x16e0 };
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+VECT_VAR_DECL(expected, uint, 16, 8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+
+#include "vmlXl_high.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_lane.c
new file mode 100644
index 0000000000000000000000000000000000000000..babe10a8934785790b136e6dba79ca1d2689807e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_lane.c
@@ -0,0 +1,20 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl_high_lane
+#define TEST_MSG "VMLSL_HIGH_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+
+#include "vmlXl_high_lane.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_laneq.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_laneq.c
new file mode 100644
index 0000000000000000000000000000000000000000..a4f35a389fbfafa01971dbd618b1ad2aa48d82fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_laneq.c
@@ -0,0 +1,20 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl_high_laneq
+#define TEST_MSG "VMLSL_HIGH_LANEQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+
+#include "vmlXl_high_laneq.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_n.c
new file mode 100644
index 0000000000000000000000000000000000000000..2b2bd8d372c1cd0f68cbd73ad5238af61da2d331
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_n.c
@@ -0,0 +1,20 @@
+/* { dg-skip-if "" { arm*-*-* } } */
+
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl_high_n
+#define TEST_MSG "VMLSL_HIGH_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected, int, 32, 4) [] = { 0xfffffa4b, 0xfffffa4c,
+ 0xfffffa4d, 0xfffffa4e };
+VECT_VAR_DECL(expected, int, 64, 2) [] = { 0xfffffffffffff4a6,
+ 0xfffffffffffff4a7 };
+VECT_VAR_DECL(expected, uint, 32, 4) [] = { 0xffffef01, 0xffffef02,
+ 0xffffef03, 0xffffef04 };
+VECT_VAR_DECL(expected, uint, 64, 2) [] = { 0xffffffffffffef01,
+ 0xffffffffffffef02 };
+
+#include "vmlXl_high_n.inc"
