Re: [PATCH,rs6000] Fusion patterns for logical-logical

[Aaron Sawdey via Gcc-patches]

Ping.

Aaron Sawdey, Ph.D. saw...@linux.ibm.com
IBM Linux on POWER Toolchain
 

> On Jan 3, 2021, at 2:43 PM, Aaron Sawdey <acsaw...@linux.ibm.com> wrote:
> 
> Ping.
> 
> Aaron Sawdey, Ph.D. saw...@linux.ibm.com
> IBM Linux on POWER Toolchain
> 
> 
>> On Dec 10, 2020, at 8:41 PM, acsaw...@linux.ibm.com wrote:
>> 
>> From: Aaron Sawdey <acsaw...@linux.ibm.com>
>> 
>> This patch adds a new function to genfusion.pl to generate patterns for
>> logical-logical fusion. They are enabled by default for power10 and can
>> be disabled by -mno-power10-fusion-2logical or -mno-power10-fusion.
>> 
>> This patch builds on top of the load-cmpi patch posted earlier this week.
>> 
>> Bootstrap passed on ppc64le/power10, if regtests pass, ok for trunk?
>> 
>> gcc/ChangeLog
>>      * config/rs6000/genfusion.pl (gen_2logical): New function to
>>      generate patterns for logical-logical fusion.
>>      * config/rs6000/fusion.md: Regenerated patterns.
>>      * config/rs6000/rs6000-cpus.def: Add
>>      OPTION_MASK_P10_FUSION_2LOGICAL.
>>      * config/rs6000/rs6000.c (rs6000_option_override_internal):
>>      Enable logical-logical fusion for p10.
>>      * config/rs6000/rs6000.opt: Add -mpower10-fusion-2logical.
>> ---
>> gcc/config/rs6000/fusion.md       | 2176 +++++++++++++++++++++++++++++
>> gcc/config/rs6000/genfusion.pl    |   89 ++
>> gcc/config/rs6000/rs6000-cpus.def |    4 +-
>> gcc/config/rs6000/rs6000.c        |    3 +
>> gcc/config/rs6000/rs6000.opt      |    4 +
>> 5 files changed, 2275 insertions(+), 1 deletion(-)
>> 
>> diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
>> index a4d3a6ae7f3..1ddbe7fe3d2 100644
>> --- a/gcc/config/rs6000/fusion.md
>> +++ b/gcc/config/rs6000/fusion.md
>> @@ -355,3 +355,2179 @@ (define_insn_and_split 
>> "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero"
>>   (set_attr "cost" "8")
>>   (set_attr "length" "8")])
>> 
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;and %3,%3,%2
>> +   and %0,%1,%0\;and %0,%0,%2
>> +   and %1,%1,%0\;and %1,%1,%2
>> +   and %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;and %3,%3,%2
>> +   andc %0,%1,%0\;and %0,%0,%2
>> +   andc %1,%1,%0\;and %1,%1,%2
>> +   andc %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;and %3,%3,%2
>> +   eqv %0,%1,%0\;and %0,%0,%2
>> +   eqv %1,%1,%0\;and %1,%1,%2
>> +   eqv %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;and %3,%3,%2
>> +   nand %0,%1,%0\;and %0,%0,%2
>> +   nand %1,%1,%0\;and %1,%1,%2
>> +   nand %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;and %3,%3,%2
>> +   nor %0,%1,%0\;and %0,%0,%2
>> +   nor %1,%1,%0\;and %1,%1,%2
>> +   nor %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;and %3,%3,%2
>> +   or %0,%1,%0\;and %0,%0,%2
>> +   or %1,%1,%0\;and %1,%1,%2
>> +   or %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;and %3,%3,%2
>> +   orc %0,%1,%0\;and %0,%0,%2
>> +   orc %1,%1,%0\;and %1,%1,%2
>> +   orc %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: and op and rtl and inv 0 comp 0
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_and"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;and %3,%3,%2
>> +   xor %0,%1,%0\;and %0,%0,%2
>> +   xor %1,%1,%0\;and %1,%1,%2
>> +   xor %4,%1,%0\;and %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;andc %3,%3,%2
>> +   and %0,%1,%0\;andc %0,%0,%2
>> +   and %1,%1,%0\;andc %1,%1,%2
>> +   and %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;andc %3,%3,%2
>> +   andc %0,%1,%0\;andc %0,%0,%2
>> +   andc %1,%1,%0\;andc %1,%1,%2
>> +   andc %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;andc %3,%3,%2
>> +   eqv %0,%1,%0\;andc %0,%0,%2
>> +   eqv %1,%1,%0\;andc %1,%1,%2
>> +   eqv %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;andc %3,%3,%2
>> +   nand %0,%1,%0\;andc %0,%0,%2
>> +   nand %1,%1,%0\;andc %1,%1,%2
>> +   nand %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;andc %3,%3,%2
>> +   nor %0,%1,%0\;andc %0,%0,%2
>> +   nor %1,%1,%0\;andc %1,%1,%2
>> +   nor %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;andc %3,%3,%2
>> +   or %0,%1,%0\;andc %0,%0,%2
>> +   or %1,%1,%0\;andc %1,%1,%2
>> +   or %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;andc %3,%3,%2
>> +   orc %0,%1,%0\;andc %0,%0,%2
>> +   orc %1,%1,%0\;andc %1,%1,%2
>> +   orc %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_andc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;andc %3,%3,%2
>> +   xor %0,%1,%0\;andc %0,%0,%2
>> +   xor %1,%1,%0\;andc %1,%1,%2
>> +   xor %4,%1,%0\;andc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;eqv %3,%3,%2
>> +   and %0,%1,%0\;eqv %0,%0,%2
>> +   and %1,%1,%0\;eqv %1,%1,%2
>> +   and %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;eqv %3,%3,%2
>> +   andc %0,%1,%0\;eqv %0,%0,%2
>> +   andc %1,%1,%0\;eqv %1,%1,%2
>> +   andc %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" 
>> "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;eqv %3,%3,%2
>> +   eqv %0,%1,%0\;eqv %0,%0,%2
>> +   eqv %1,%1,%0\;eqv %1,%1,%2
>> +   eqv %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 
>> "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" 
>> "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;eqv %3,%3,%2
>> +   nand %0,%1,%0\;eqv %0,%0,%2
>> +   nand %1,%1,%0\;eqv %1,%1,%2
>> +   nand %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 
>> "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" 
>> "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;eqv %3,%3,%2
>> +   nor %0,%1,%0\;eqv %0,%0,%2
>> +   nor %1,%1,%0\;eqv %1,%1,%2
>> +   nor %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;eqv %3,%3,%2
>> +   or %0,%1,%0\;eqv %0,%0,%2
>> +   or %1,%1,%0\;eqv %1,%1,%2
>> +   or %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;eqv %3,%3,%2
>> +   orc %0,%1,%0\;eqv %0,%0,%2
>> +   orc %1,%1,%0\;eqv %1,%1,%2
>> +   orc %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_eqv"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;eqv %3,%3,%2
>> +   xor %0,%1,%0\;eqv %0,%0,%2
>> +   xor %1,%1,%0\;eqv %1,%1,%2
>> +   xor %4,%1,%0\;eqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;nand %3,%3,%2
>> +   and %0,%1,%0\;nand %0,%0,%2
>> +   and %1,%1,%0\;nand %1,%1,%2
>> +   and %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;nand %3,%3,%2
>> +   andc %0,%1,%0\;nand %0,%0,%2
>> +   andc %1,%1,%0\;nand %1,%1,%2
>> +   andc %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;nand %3,%3,%2
>> +   eqv %0,%1,%0\;nand %0,%0,%2
>> +   eqv %1,%1,%0\;nand %1,%1,%2
>> +   eqv %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 
>> "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;nand %3,%3,%2
>> +   nand %0,%1,%0\;nand %0,%0,%2
>> +   nand %1,%1,%0\;nand %1,%1,%2
>> +   nand %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 
>> "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;nand %3,%3,%2
>> +   nor %0,%1,%0\;nand %0,%0,%2
>> +   nor %1,%1,%0\;nand %1,%1,%2
>> +   nor %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;nand %3,%3,%2
>> +   or %0,%1,%0\;nand %0,%0,%2
>> +   or %1,%1,%0\;nand %1,%1,%2
>> +   or %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;nand %3,%3,%2
>> +   orc %0,%1,%0\;nand %0,%0,%2
>> +   orc %1,%1,%0\;nand %1,%1,%2
>> +   orc %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_nand"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;nand %3,%3,%2
>> +   xor %0,%1,%0\;nand %0,%0,%2
>> +   xor %1,%1,%0\;nand %1,%1,%2
>> +   xor %4,%1,%0\;nand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;nor %3,%3,%2
>> +   and %0,%1,%0\;nor %0,%0,%2
>> +   and %1,%1,%0\;nor %1,%1,%2
>> +   and %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;nor %3,%3,%2
>> +   andc %0,%1,%0\;nor %0,%0,%2
>> +   andc %1,%1,%0\;nor %1,%1,%2
>> +   andc %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;nor %3,%3,%2
>> +   eqv %0,%1,%0\;nor %0,%0,%2
>> +   eqv %1,%1,%0\;nor %1,%1,%2
>> +   eqv %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 
>> "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;nor %3,%3,%2
>> +   nand %0,%1,%0\;nor %0,%0,%2
>> +   nand %1,%1,%0\;nor %1,%1,%2
>> +   nand %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 
>> "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;nor %3,%3,%2
>> +   nor %0,%1,%0\;nor %0,%0,%2
>> +   nor %1,%1,%0\;nor %1,%1,%2
>> +   nor %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;nor %3,%3,%2
>> +   or %0,%1,%0\;nor %0,%0,%2
>> +   or %1,%1,%0\;nor %1,%1,%2
>> +   or %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 
>> "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" 
>> "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;nor %3,%3,%2
>> +   orc %0,%1,%0\;nor %0,%0,%2
>> +   orc %1,%1,%0\;nor %1,%1,%2
>> +   orc %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_nor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;nor %3,%3,%2
>> +   xor %0,%1,%0\;nor %0,%0,%2
>> +   xor %1,%1,%0\;nor %1,%1,%2
>> +   xor %4,%1,%0\;nor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;or %3,%3,%2
>> +   and %0,%1,%0\;or %0,%0,%2
>> +   and %1,%1,%0\;or %1,%1,%2
>> +   and %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;or %3,%3,%2
>> +   andc %0,%1,%0\;or %0,%0,%2
>> +   andc %1,%1,%0\;or %1,%1,%2
>> +   andc %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;or %3,%3,%2
>> +   eqv %0,%1,%0\;or %0,%0,%2
>> +   eqv %1,%1,%0\;or %1,%1,%2
>> +   eqv %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;or %3,%3,%2
>> +   nand %0,%1,%0\;or %0,%0,%2
>> +   nand %1,%1,%0\;or %1,%1,%2
>> +   nand %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;or %3,%3,%2
>> +   nor %0,%1,%0\;or %0,%0,%2
>> +   nor %1,%1,%0\;or %1,%1,%2
>> +   nor %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;or %3,%3,%2
>> +   or %0,%1,%0\;or %0,%0,%2
>> +   or %1,%1,%0\;or %1,%1,%2
>> +   or %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;or %3,%3,%2
>> +   orc %0,%1,%0\;or %0,%0,%2
>> +   orc %1,%1,%0\;or %1,%1,%2
>> +   orc %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: or op or rtl ior inv 0 comp 0
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_or"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;or %3,%3,%2
>> +   xor %0,%1,%0\;or %0,%0,%2
>> +   xor %1,%1,%0\;or %1,%1,%2
>> +   xor %4,%1,%0\;or %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;orc %3,%3,%2
>> +   and %0,%1,%0\;orc %0,%0,%2
>> +   and %1,%1,%0\;orc %1,%1,%2
>> +   and %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;orc %3,%3,%2
>> +   andc %0,%1,%0\;orc %0,%0,%2
>> +   andc %1,%1,%0\;orc %1,%1,%2
>> +   andc %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;orc %3,%3,%2
>> +   eqv %0,%1,%0\;orc %0,%0,%2
>> +   eqv %1,%1,%0\;orc %1,%1,%2
>> +   eqv %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;orc %3,%3,%2
>> +   nand %0,%1,%0\;orc %0,%0,%2
>> +   nand %1,%1,%0\;orc %1,%1,%2
>> +   nand %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;orc %3,%3,%2
>> +   nor %0,%1,%0\;orc %0,%0,%2
>> +   nor %1,%1,%0\;orc %1,%1,%2
>> +   nor %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;orc %3,%3,%2
>> +   or %0,%1,%0\;orc %0,%0,%2
>> +   or %1,%1,%0\;orc %1,%1,%2
>> +   or %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;orc %3,%3,%2
>> +   orc %0,%1,%0\;orc %0,%0,%2
>> +   orc %1,%1,%0\;orc %1,%1,%2
>> +   orc %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_orc"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;orc %3,%3,%2
>> +   xor %0,%1,%0\;orc %0,%0,%2
>> +   xor %1,%1,%0\;orc %1,%1,%2
>> +   xor %4,%1,%0\;orc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: and op and rtl and inv 0 comp 0
>> +(define_insn "*fuse_and_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   and %3,%1,%0\;xor %3,%3,%2
>> +   and %0,%1,%0\;xor %0,%0,%2
>> +   and %1,%1,%0\;xor %1,%1,%2
>> +   and %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: andc op andc rtl and inv 0 comp 1
>> +(define_insn "*fuse_andc_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   andc %3,%1,%0\;xor %3,%3,%2
>> +   andc %0,%1,%0\;xor %0,%0,%2
>> +   andc %1,%1,%0\;xor %1,%1,%2
>> +   andc %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: eqv op eqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_eqv_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   eqv %3,%1,%0\;xor %3,%3,%2
>> +   eqv %0,%1,%0\;xor %0,%0,%2
>> +   eqv %1,%1,%0\;xor %1,%1,%2
>> +   eqv %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: nand op nand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_nand_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nand %3,%1,%0\;xor %3,%3,%2
>> +   nand %0,%1,%0\;xor %0,%0,%2
>> +   nand %1,%1,%0\;xor %1,%1,%2
>> +   nand %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: nor op nor rtl and inv 0 comp 3
>> +(define_insn "*fuse_nor_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   nor %3,%1,%0\;xor %3,%3,%2
>> +   nor %0,%1,%0\;xor %0,%0,%2
>> +   nor %1,%1,%0\;xor %1,%1,%2
>> +   nor %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: or op or rtl ior inv 0 comp 0
>> +(define_insn "*fuse_or_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   or %3,%1,%0\;xor %3,%3,%2
>> +   or %0,%1,%0\;xor %0,%0,%2
>> +   or %1,%1,%0\;xor %1,%1,%2
>> +   or %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: orc op orc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_orc_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" 
>> "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 
>> (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   orc %3,%1,%0\;xor %3,%3,%2
>> +   orc %0,%1,%0\;xor %0,%0,%2
>> +   orc %1,%1,%0\;xor %1,%1,%2
>> +   orc %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0
>> +;; inner: xor op xor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_xor_xor"
>> +  [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r")
>> +        (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 
>> (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 
>> "gpc_reg_operand" "r,r,r,r")))
>> +   (clobber (match_scratch:GPR 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   xor %3,%1,%0\;xor %3,%3,%2
>> +   xor %0,%1,%0\;xor %0,%0,%2
>> +   xor %1,%1,%0\;xor %1,%1,%2
>> +   xor %4,%1,%0\;xor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vand %3,%3,%2
>> +   vand %0,%1,%0\;vand %0,%0,%2
>> +   vand %1,%1,%0\;vand %1,%1,%2
>> +   vand %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vand %3,%3,%2
>> +   vandc %0,%1,%0\;vand %0,%0,%2
>> +   vandc %1,%1,%0\;vand %1,%1,%2
>> +   vandc %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vand %3,%3,%2
>> +   veqv %0,%1,%0\;vand %0,%0,%2
>> +   veqv %1,%1,%0\;vand %1,%1,%2
>> +   veqv %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vand %3,%3,%2
>> +   vnand %0,%1,%0\;vand %0,%0,%2
>> +   vnand %1,%1,%0\;vand %1,%1,%2
>> +   vnand %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vand %3,%3,%2
>> +   vnor %0,%1,%0\;vand %0,%0,%2
>> +   vnor %1,%1,%0\;vand %1,%1,%2
>> +   vnor %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vand %3,%3,%2
>> +   vor %0,%1,%0\;vand %0,%0,%2
>> +   vor %1,%1,%0\;vand %1,%1,%2
>> +   vor %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vand %3,%3,%2
>> +   vorc %0,%1,%0\;vand %0,%0,%2
>> +   vorc %1,%1,%0\;vand %1,%1,%2
>> +   vorc %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: and op vand rtl and inv 0 comp 0
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vand %3,%3,%2
>> +   vxor %0,%1,%0\;vand %0,%0,%2
>> +   vxor %1,%1,%0\;vand %1,%1,%2
>> +   vxor %4,%1,%0\;vand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vandc %3,%3,%2
>> +   vand %0,%1,%0\;vandc %0,%0,%2
>> +   vand %1,%1,%0\;vandc %1,%1,%2
>> +   vand %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vandc %3,%3,%2
>> +   vandc %0,%1,%0\;vandc %0,%0,%2
>> +   vandc %1,%1,%0\;vandc %1,%1,%2
>> +   vandc %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vandc %3,%3,%2
>> +   veqv %0,%1,%0\;vandc %0,%0,%2
>> +   veqv %1,%1,%0\;vandc %1,%1,%2
>> +   veqv %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vandc %3,%3,%2
>> +   vnand %0,%1,%0\;vandc %0,%0,%2
>> +   vnand %1,%1,%0\;vandc %1,%1,%2
>> +   vnand %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vandc %3,%3,%2
>> +   vnor %0,%1,%0\;vandc %0,%0,%2
>> +   vnor %1,%1,%0\;vandc %1,%1,%2
>> +   vnor %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vandc %3,%3,%2
>> +   vor %0,%1,%0\;vandc %0,%0,%2
>> +   vor %1,%1,%0\;vandc %1,%1,%2
>> +   vor %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vandc %3,%3,%2
>> +   vorc %0,%1,%0\;vandc %0,%0,%2
>> +   vorc %1,%1,%0\;vandc %1,%1,%2
>> +   vorc %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vandc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vandc %3,%3,%2
>> +   vxor %0,%1,%0\;vandc %0,%0,%2
>> +   vxor %1,%1,%0\;vandc %1,%1,%2
>> +   vxor %4,%1,%0\;vandc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (and:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;veqv %3,%3,%2
>> +   vand %0,%1,%0\;veqv %0,%0,%2
>> +   vand %1,%1,%0\;veqv %1,%1,%2
>> +   vand %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;veqv %3,%3,%2
>> +   vandc %0,%1,%0\;veqv %0,%0,%2
>> +   vandc %1,%1,%0\;veqv %1,%1,%2
>> +   vandc %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;veqv %3,%3,%2
>> +   veqv %0,%1,%0\;veqv %0,%0,%2
>> +   veqv %1,%1,%0\;veqv %1,%1,%2
>> +   veqv %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;veqv %3,%3,%2
>> +   vnand %0,%1,%0\;veqv %0,%0,%2
>> +   vnand %1,%1,%0\;veqv %1,%1,%2
>> +   vnand %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;veqv %3,%3,%2
>> +   vnor %0,%1,%0\;veqv %0,%0,%2
>> +   vnor %1,%1,%0\;veqv %1,%1,%2
>> +   vnor %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (ior:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;veqv %3,%3,%2
>> +   vor %0,%1,%0\;veqv %0,%0,%2
>> +   vor %1,%1,%0\;veqv %1,%1,%2
>> +   vor %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;veqv %3,%3,%2
>> +   vorc %0,%1,%0\;veqv %0,%0,%2
>> +   vorc %1,%1,%0\;veqv %1,%1,%2
>> +   vorc %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_veqv"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (not:VM (xor:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;veqv %3,%3,%2
>> +   vxor %0,%1,%0\;veqv %0,%0,%2
>> +   vxor %1,%1,%0\;veqv %1,%1,%2
>> +   vxor %4,%1,%0\;veqv %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (and:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vnand %3,%3,%2
>> +   vand %0,%1,%0\;vnand %0,%0,%2
>> +   vand %1,%1,%0\;vnand %1,%1,%2
>> +   vand %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vnand %3,%3,%2
>> +   vandc %0,%1,%0\;vnand %0,%0,%2
>> +   vandc %1,%1,%0\;vnand %1,%1,%2
>> +   vandc %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vnand %3,%3,%2
>> +   veqv %0,%1,%0\;vnand %0,%0,%2
>> +   veqv %1,%1,%0\;vnand %1,%1,%2
>> +   veqv %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vnand %3,%3,%2
>> +   vnand %0,%1,%0\;vnand %0,%0,%2
>> +   vnand %1,%1,%0\;vnand %1,%1,%2
>> +   vnand %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vnand %3,%3,%2
>> +   vnor %0,%1,%0\;vnand %0,%0,%2
>> +   vnor %1,%1,%0\;vnand %1,%1,%2
>> +   vnor %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (ior:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vnand %3,%3,%2
>> +   vor %0,%1,%0\;vnand %0,%0,%2
>> +   vor %1,%1,%0\;vnand %1,%1,%2
>> +   vor %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vnand %3,%3,%2
>> +   vorc %0,%1,%0\;vnand %0,%0,%2
>> +   vorc %1,%1,%0\;vnand %1,%1,%2
>> +   vorc %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vnand"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vnand %3,%3,%2
>> +   vxor %0,%1,%0\;vnand %0,%0,%2
>> +   vxor %1,%1,%0\;vnand %1,%1,%2
>> +   vxor %4,%1,%0\;vnand %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (and:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vnor %3,%3,%2
>> +   vand %0,%1,%0\;vnor %0,%0,%2
>> +   vand %1,%1,%0\;vnor %1,%1,%2
>> +   vand %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vnor %3,%3,%2
>> +   vandc %0,%1,%0\;vnor %0,%0,%2
>> +   vandc %1,%1,%0\;vnor %1,%1,%2
>> +   vandc %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vnor %3,%3,%2
>> +   veqv %0,%1,%0\;vnor %0,%0,%2
>> +   veqv %1,%1,%0\;vnor %1,%1,%2
>> +   veqv %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vnor %3,%3,%2
>> +   vnand %0,%1,%0\;vnor %0,%0,%2
>> +   vnand %1,%1,%0\;vnor %1,%1,%2
>> +   vnand %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vnor %3,%3,%2
>> +   vnor %0,%1,%0\;vnor %0,%0,%2
>> +   vnor %1,%1,%0\;vnor %1,%1,%2
>> +   vnor %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (ior:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vnor %3,%3,%2
>> +   vor %0,%1,%0\;vnor %0,%0,%2
>> +   vor %1,%1,%0\;vnor %1,%1,%2
>> +   vor %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vnor %3,%3,%2
>> +   vorc %0,%1,%0\;vnor %0,%0,%2
>> +   vorc %1,%1,%0\;vnor %1,%1,%2
>> +   vorc %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vnor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (and:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vnor %3,%3,%2
>> +   vxor %0,%1,%0\;vnor %0,%0,%2
>> +   vxor %1,%1,%0\;vnor %1,%1,%2
>> +   vxor %4,%1,%0\;vnor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vor %3,%3,%2
>> +   vand %0,%1,%0\;vor %0,%0,%2
>> +   vand %1,%1,%0\;vor %1,%1,%2
>> +   vand %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vor %3,%3,%2
>> +   vandc %0,%1,%0\;vor %0,%0,%2
>> +   vandc %1,%1,%0\;vor %1,%1,%2
>> +   vandc %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vor %3,%3,%2
>> +   veqv %0,%1,%0\;vor %0,%0,%2
>> +   veqv %1,%1,%0\;vor %1,%1,%2
>> +   veqv %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vor %3,%3,%2
>> +   vnand %0,%1,%0\;vor %0,%0,%2
>> +   vnand %1,%1,%0\;vor %1,%1,%2
>> +   vnand %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vor %3,%3,%2
>> +   vnor %0,%1,%0\;vor %0,%0,%2
>> +   vnor %1,%1,%0\;vor %1,%1,%2
>> +   vnor %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vor %3,%3,%2
>> +   vor %0,%1,%0\;vor %0,%0,%2
>> +   vor %1,%1,%0\;vor %1,%1,%2
>> +   vor %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vor %3,%3,%2
>> +   vorc %0,%1,%0\;vor %0,%0,%2
>> +   vorc %1,%1,%0\;vor %1,%1,%2
>> +   vorc %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: or op vor rtl ior inv 0 comp 0
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vor %3,%3,%2
>> +   vxor %0,%1,%0\;vor %0,%0,%2
>> +   vxor %1,%1,%0\;vor %1,%1,%2
>> +   vxor %4,%1,%0\;vor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vorc %3,%3,%2
>> +   vand %0,%1,%0\;vorc %0,%0,%2
>> +   vand %1,%1,%0\;vorc %1,%1,%2
>> +   vand %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vorc %3,%3,%2
>> +   vandc %0,%1,%0\;vorc %0,%0,%2
>> +   vandc %1,%1,%0\;vorc %1,%1,%2
>> +   vandc %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vorc %3,%3,%2
>> +   veqv %0,%1,%0\;vorc %0,%0,%2
>> +   veqv %1,%1,%0\;vorc %1,%1,%2
>> +   veqv %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vorc %3,%3,%2
>> +   vnand %0,%1,%0\;vorc %0,%0,%2
>> +   vnand %1,%1,%0\;vorc %1,%1,%2
>> +   vnand %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vorc %3,%3,%2
>> +   vnor %0,%1,%0\;vorc %0,%0,%2
>> +   vnor %1,%1,%0\;vorc %1,%1,%2
>> +   vnor %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vorc %3,%3,%2
>> +   vor %0,%1,%0\;vorc %0,%0,%2
>> +   vor %1,%1,%0\;vorc %1,%1,%2
>> +   vor %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vorc %3,%3,%2
>> +   vorc %0,%1,%0\;vorc %0,%0,%2
>> +   vorc %1,%1,%0\;vorc %1,%1,%2
>> +   vorc %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vorc"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vorc %3,%3,%2
>> +   vxor %0,%1,%0\;vorc %0,%0,%2
>> +   vxor %1,%1,%0\;vorc %1,%1,%2
>> +   vxor %4,%1,%0\;vorc %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: and op vand rtl and inv 0 comp 0
>> +(define_insn "*fuse_vand_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vand %3,%1,%0\;vxor %3,%3,%2
>> +   vand %0,%1,%0\;vxor %0,%0,%2
>> +   vand %1,%1,%0\;vxor %1,%1,%2
>> +   vand %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: andc op vandc rtl and inv 0 comp 1
>> +(define_insn "*fuse_vandc_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vandc %3,%1,%0\;vxor %3,%3,%2
>> +   vandc %0,%1,%0\;vxor %0,%0,%2
>> +   vandc %1,%1,%0\;vxor %1,%1,%2
>> +   vandc %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: eqv op veqv rtl xor inv 1 comp 0
>> +(define_insn "*fuse_veqv_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (not:VM (xor:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   veqv %3,%1,%0\;vxor %3,%3,%2
>> +   veqv %0,%1,%0\;vxor %0,%0,%2
>> +   veqv %1,%1,%0\;vxor %1,%1,%2
>> +   veqv %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: nand op vnand rtl ior inv 0 comp 3
>> +(define_insn "*fuse_vnand_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnand %3,%1,%0\;vxor %3,%3,%2
>> +   vnand %0,%1,%0\;vxor %0,%0,%2
>> +   vnand %1,%1,%0\;vxor %1,%1,%2
>> +   vnand %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: nor op vnor rtl and inv 0 comp 3
>> +(define_insn "*fuse_vnor_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (and:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vnor %3,%1,%0\;vxor %3,%3,%2
>> +   vnor %0,%1,%0\;vxor %0,%0,%2
>> +   vnor %1,%1,%0\;vxor %1,%1,%2
>> +   vnor %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: or op vor rtl ior inv 0 comp 0
>> +(define_insn "*fuse_vor_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vor %3,%1,%0\;vxor %3,%3,%2
>> +   vor %0,%1,%0\;vxor %0,%0,%2
>> +   vor %1,%1,%0\;vxor %1,%1,%2
>> +   vor %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: orc op vorc rtl ior inv 0 comp 1
>> +(define_insn "*fuse_vorc_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (ior:VM (not:VM (match_operand:VM 0 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 
>> "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 
>> "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vorc %3,%1,%0\;vxor %3,%3,%2
>> +   vorc %0,%1,%0\;vxor %0,%0,%2
>> +   vorc %1,%1,%0\;vxor %1,%1,%2
>> +   vorc %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0
>> +;; inner: xor op vxor rtl xor inv 0 comp 0
>> +(define_insn "*fuse_vxor_vxor"
>> +  [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v")
>> +        (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" 
>> "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 
>> (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))
>> +   (clobber (match_scratch:VM 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   vxor %3,%1,%0\;vxor %3,%3,%2
>> +   vxor %0,%1,%0\;vxor %0,%0,%2
>> +   vxor %1,%1,%0\;vxor %1,%1,%2
>> +   vxor %4,%1,%0\;vxor %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
>> index 494537c9439..06bce3c43a4 100755
>> --- a/gcc/config/rs6000/genfusion.pl
>> +++ b/gcc/config/rs6000/genfusion.pl
>> @@ -137,8 +137,97 @@ sub gen_ld_cmpi_p10
>>  }
>> }
>> 
>> +sub gen_2logical
>> +{
>> +    my @logicals = ( "and", "andc", "eqv", "nand", "nor", "or", "orc", 
>> "xor" );
>> +    my %complement = ( "and"=> 0, "andc"=> 1, "eqv"=> 0, "nand"=> 3,
>> +                   "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0 );
>> +    my %invert = ( "and"=> 0, "andc"=> 0, "eqv"=> 1, "nand"=> 0,
>> +               "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0 );
>> +    my %commute2 = ( "and"=> 1, "andc"=> 0, "eqv"=> 1, "nand"=> 0,
>> +                 "nor"=> 0, "or"=> 1, "orc"=> 0, "xor"=> 1 );
>> +    my %rtlop = ( "and"=>"and", "andc"=>"and", "eqv"=>"xor", "nand"=>"ior",
>> +              "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor" );
>> +
>> +  KIND: foreach $kind ('scalar','vector') {
>> +      if ( $kind eq 'vector' ) {
>> +      $vchr = "v";
>> +      $mode = "VM";
>> +      $pred = "altivec_register_operand";
>> +      $constraint = "v";
>> +      } else {
>> +      $vchr = "";
>> +      $mode = "GPR";
>> +      $pred = "gpc_reg_operand";
>> +      $constraint = "r";
>> +      }
>> +      $c4 = "${constraint},${constraint},${constraint},${constraint}";
>> +    OUTER: foreach $outer ( @logicals ) {
>> +    $outer_op = "${vchr}${outer}";
>> +    $outer_comp = $complement{$outer};
>> +    $outer_inv = $invert{$outer};
>> +    $outer_rtl = $rtlop{$outer};
>> +      INNER: foreach $inner ( @logicals ) {
>> +      $inner_comp = $complement{$inner};
>> +      $inner_inv = $invert{$inner};
>> +      $inner_rtl = $rtlop{$inner};
>> +      $inner_op = "${vchr}${inner}";
>> +      # If both ops commute then we can specify % on operand 1
>> +      # so the pattern will let operands 1 and 2 interchange.
>> +      $both_commute = ($inner eq $outer) && ($commute2{$inner} == 1);
>> +      $bc = ""; if ( $both_commute ) { $bc = "%"; }
>> +      $inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")";
>> +      $inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")";
>> +      if ( ($inner_comp & 1) == 1 ) {
>> +          $inner_arg0 = "(not:${mode} $inner_arg0)";
>> +      }
>> +      if ( ($inner_comp & 2) == 2 ) {
>> +          $inner_arg1 = "(not:${mode} $inner_arg1)";
>> +      }
>> +      $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})";
>> +      if ( $inner_inv == 1 ) {
>> +          $inner_exp = "(not:${mode} $inner_exp)";
>> +      }
>> +      $outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")";
>> +      if ( ($outer_comp & 1) == 1 ) {
>> +          $outer_arg2 = "(not:${mode} $outer_arg2)";
>> +      }
>> +      if ( ($outer_comp & 2) == 2 ) {
>> +          $inner_exp = "(not:${mode} $inner_exp)";
>> +      }
>> +      $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})";
>> +      if ( $outer_inv == 1 ) {
>> +          $outer_exp = "(not:${mode} $outer_exp)";
>> +      }
>> +
>> +      $insn =  <<"EOF";
>> +
>> +;; logical-logical fusion pattern generated by gen_2logical
>> +;; kind: $kind outer: $outer op $outer_op rtl $outer_rtl inv $outer_inv 
>> comp $outer_comp
>> +;; inner: $inner op $inner_op rtl $inner_rtl inv $inner_inv comp $inner_comp
>> +(define_insn "*fuse_${inner_op}_${outer_op}"
>> +  [(set (match_operand:${mode} 3 "${pred}" 
>> "=&${constraint},0,1,${constraint}")
>> +        ${outer_exp})
>> +   (clobber (match_scratch:${mode} 4 "=X,X,X,r"))]
>> +  "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)"
>> +  "@
>> +   ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
>> +   ${inner_op} %0,%1,%0\\;${outer_op} %0,%0,%2
>> +   ${inner_op} %1,%1,%0\\;${outer_op} %1,%1,%2
>> +   ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
>> +  [(set_attr "type" "logical")
>> +   (set_attr "cost" "6")
>> +   (set_attr "length" "8")])
>> +EOF
>> +
>> +      print $insn;
>> +      }
>> +    }
>> +  }
>> +}
>> 
>> gen_ld_cmpi_p10();
>> +gen_2logical();
>> 
>> exit(0);
>> 
>> diff --git a/gcc/config/rs6000/rs6000-cpus.def 
>> b/gcc/config/rs6000/rs6000-cpus.def
>> index 3e65289d8df..a09a760daa9 100644
>> --- a/gcc/config/rs6000/rs6000-cpus.def
>> +++ b/gcc/config/rs6000/rs6000-cpus.def
>> @@ -84,7 +84,8 @@
>>                               | OPTION_MASK_POWER10                  \
>>                               | OTHER_POWER10_MASKS                  \
>>                               | OPTION_MASK_P10_FUSION               \
>> -                             | OPTION_MASK_P10_FUSION_LD_CMPI)
>> +                             | OPTION_MASK_P10_FUSION_LD_CMPI       \
>> +                             | OPTION_MASK_P10_FUSION_2LOGICAL)
>> 
>> /* Flags that need to be turned off if -mno-power9-vector.  */
>> #define OTHER_P9_VECTOR_MASKS        (OPTION_MASK_FLOAT128_HW                
>> \
>> @@ -133,6 +134,7 @@
>>                               | OPTION_MASK_POWER10                  \
>>                               | OPTION_MASK_P10_FUSION               \
>>                               | OPTION_MASK_P10_FUSION_LD_CMPI       \
>> +                             | OPTION_MASK_P10_FUSION_2LOGICAL      \
>>                               | OPTION_MASK_HTM                      \
>>                               | OPTION_MASK_ISEL                     \
>>                               | OPTION_MASK_MFCRF                    \
>> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
>> index 759551d07ec..7c043a22128 100644
>> --- a/gcc/config/rs6000/rs6000.c
>> +++ b/gcc/config/rs6000/rs6000.c
>> @@ -4429,6 +4429,9 @@ rs6000_option_override_internal (bool global_init_p)
>>  if (TARGET_POWER10 && (rs6000_isa_flags_explicit & 
>> OPTION_MASK_P10_FUSION_LD_CMPI) == 0)
>>    rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LD_CMPI;
>> 
>> +  if (TARGET_POWER10 && (rs6000_isa_flags_explicit & 
>> OPTION_MASK_P10_FUSION_2LOGICAL) == 0)
>> +    rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL;
>> +
>>  /* Turn off vector pair/mma options on non-power10 systems.  */
>>  else if (!TARGET_POWER10 && TARGET_MMA)
>>    {
>> diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
>> index 008a318b98d..d4eecba013b 100644
>> --- a/gcc/config/rs6000/rs6000.opt
>> +++ b/gcc/config/rs6000/rs6000.opt
>> @@ -487,6 +487,10 @@ mpower10-fusion-ld-cmpi
>> Target Undocumented Mask(P10_FUSION_LD_CMPI) Var(rs6000_isa_flags)
>> Fuse certain integer operations together for better performance on power10.
>> 
>> +mpower10-fusion-2logical
>> +Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags)
>> +Fuse certain integer operations together for better performance on power10.
>> +
>> mcrypto
>> Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
>> Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
>> -- 
>> 2.27.0
>> 
>