Hi all,
following discussion on PR97092 I'd like to submit the following patch
with a fix plus associated testcase.
With this patch applied mode is recomputed at each iteration while
looping across different copies in 'update_costs_from_allocno', this
instead of carrying mode over subsequent iterations.
bootstrapped and regtested on aarch64-unknown-linux-gnu.
Okay for trunk?
Thanks!
Andrea
>From 302573854794f023d8f4ab47660f367016627340 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.cora...@arm.com>
Date: Wed, 9 Dec 2020 17:59:12 +0100
Subject: [PATCH] ira.c: Fix ICE in ira-color [PR97092]
2020-12-10 Andrea Corallo <andrea.cora...@arm.com>
gcc/ChangeLog
2020-12-10 Andrea Corallo <andrea.cora...@arm.com>
PR rtl-optimization/97092
* ira-color.c (update_costs_from_allocno): Do not carry over mode
between subsequent iterations.
gcc/testsuite/ChangeLog
2020-12-10 Andrea Corallo <andrea.cora...@arm.com>
* gcc.target/aarch64/sve/pr97092.c: New test.
---
gcc/ira-color.c | 6 +++--
.../gcc.target/aarch64/sve/pr97092.c | 24 +++++++++++++++++++
2 files changed, 28 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr97092.c
diff --git a/gcc/ira-color.c b/gcc/ira-color.c
index d3f8e23faff..eb525390494 100644
--- a/gcc/ira-color.c
+++ b/gcc/ira-color.c
@@ -1407,9 +1407,11 @@ update_costs_from_allocno (ira_allocno_t allocno, int
hard_regno,
register classes bigger modes might be invalid,
e.g. DImode for AREG on x86. For such cases the
register move cost will be maximal. */
- mode = narrower_subreg_mode (mode, ALLOCNO_MODE (cp->second));
+ mode = narrower_subreg_mode (ALLOCNO_MODE (cp->first),
+ ALLOCNO_MODE (cp->second));
+
ira_init_register_move_cost_if_necessary (mode);
-
+
cost = (cp->second == allocno
? ira_register_move_cost[mode][rclass][aclass]
: ira_register_move_cost[mode][aclass][rclass]);
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97092.c
b/gcc/testsuite/gcc.target/aarch64/sve/pr97092.c
new file mode 100644
index 00000000000..69f7a3ee2db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97092.c
@@ -0,0 +1,24 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O1 -ftree-vectorize -march=armv8.2-a+sve" } */
+
+void g (void);
+long a;
+
+signed char
+bar (int c, int d)
+{
+ return c + d;
+}
+
+void
+foo (void)
+{
+ int f;
+ for (; (long)foo < 4;) {
+ f = 0;
+ for (; f < 10; f++);
+ g ();
+ a = -4;
+ for (; a; a = bar (a, 1));
+ }
+}
--
2.20.1
