On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu <crazy...@gmail.com> wrote:
> > > gcc/ChangeLog:
> > >
> > > PR target/97194
> > > * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function.
> > > * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl.
> > > * config/i386/predicates.md (vec_setm_operand): New predicate,
> > > true for const_int_operand or register_operand under TARGET_AVX2.
> > > * config/i386/sse.md (vec_set<mode>): Support both constant
> > > and variable index vec_set.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/i386/avx2-vec-set-1.c: New test.
> > > * gcc.target/i386/avx2-vec-set-2.c: New test.
> > > * gcc.target/i386/avx512bw-vec-set-1.c: New test.
> > > * gcc.target/i386/avx512bw-vec-set-2.c: New test.
> > > * gcc.target/i386/avx512f-vec-set-2.c: New test.
> > > * gcc.target/i386/avx512vl-vec-set-2.c: New test.
> >
> > +;; True for registers, or const_int_operand, used to vec_setm expander.
> > +(define_predicate "vec_setm_operand"
> > + (ior (and (match_operand 0 "register_operand")
> > + (match_test "TARGET_AVX2"))
> > + (match_code "const_int")))
> > +
> > ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
> > (define_predicate "reg_or_pm1_operand"
> > (ior (match_operand 0 "register_operand")
> > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> > index b153a87fb98..1798e5dea75 100644
> > --- a/gcc/config/i386/sse.md
> > +++ b/gcc/config/i386/sse.md
> > @@ -8098,11 +8098,14 @@ (define_insn "vec_setv2df_0"
> > (define_expand "vec_set<mode>"
> > [(match_operand:V 0 "register_operand")
> > (match_operand:<ssescalarmode> 1 "register_operand")
> > - (match_operand 2 "const_int_operand")]
> > + (match_operand 2 "vec_setm_operand")]
> >
> > You need to specify a mode, otherwise a register of any mode can pass here.
> >
> Yes, theoretically, we only accept integer types. But in can_vec_set_var_idx_p
> cut
> ---
> bool
> can_vec_set_var_idx_p (machine_mode vec_mode)
> {
> if (!VECTOR_MODE_P (vec_mode))
> return false;
>
> machine_mode inner_mode = GET_MODE_INNER (vec_mode);
> rtx reg1 = alloca_raw_REG (vec_mode, LAST_VIRTUAL_REGISTER + 1);
> rtx reg2 = alloca_raw_REG (inner_mode, LAST_VIRTUAL_REGISTER + 2);
> rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3);
>
> enum insn_code icode = optab_handler (vec_set_optab, vec_mode);
>
> return icode != CODE_FOR_nothing && insn_operand_matches (icode, 0, reg1)
> && insn_operand_matches (icode, 1, reg2)
> && insn_operand_matches (icode, 2, reg3);
> }
> ---
>
> reg3 is assumed to be VOIDmode, set anymode in match_operand 2 will
> fail insn_operand_matches (icode, 2, reg3)
> ---
> (gdb) p insn_operand_matches(icode,2,reg3)
> $5 = false
> (gdb)
> ---
>
> Maybe we need to change
>
> rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3);
>
> to
>
> rtx reg3 = alloca_raw_REG (SImode, LAST_VIRTUAL_REGISTER + 3);
>
> cc Richard Biener, any thoughts?
There are two targets (gcn in gcn-valu.md and s390 in vector.md) that
specify SImode for operand 2 in vec_setM pattern and allow register
operands. I wonder if and how they manage to generate the pattern.
Uros.
