On 11/10/20 12:44 PM, Stefan Kanthak wrote: > Eric Botcazou <botca...@adacore.com> wrote: > >>> The implementation of the __ashlDI3(), __ashrDI3() and __lshrDI3() functions >>> is rather bad, it yields bad machine code at least on i386 and AMD64. Since >>> GCC knows how to shift integers twice the register size these functions can >>> be written as one-liners. >> These functions are precisely meant to be used when GCC cannot do that. > On which processor(s) is GCC unable to generate code for DWtype shifts?
We'd have to look at them all, and it's just not worth the headache. Just to pick one off the top of my head that I know well would be the H8 which only has QI, HI and SI shifts/rotates. I'd expect inherent support for double-word shifts to be the exception rather than the rule for 32bit embedded targets. > > JFTR: if GCC were not able to generate code for DWtype addition and > subtraction > it would also need __[u]addDI3() and __[u]subDI3() functions ... which > are but missing from libgcc.a Umm, no. Non-overflow trapping addition/subtraction needs just one version, signedness doesn't matter. jeff
