The following patch fixes failures for test p9-extract-2.c on
ppc64. The failures are a result of committing patch dealing with insn
scratches in IRA. The pseudo corresponding the 1st scratch in the
following insn get unexpected register class (general regs) and
unexpected insn alternative (the 2nd one).
;; Optimize stores to use the ISA 3.0 scalar store instructions
(define_insn_and_split "*vsx_extract_<mode>_store_p9"
[(set (match_operand:<VS_scalar> 0 "memory_operand" "=Z,m")
(vec_select:<VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>,v")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))
(clobber (match_scratch:<VS_scalar> 3 "=<VSX_EX>,&r"))
(clobber (match_scratch:SI 4 "=X,&r"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
Actually getting the right hard register in LRA before the patch was a luck.
The following patch fixes the failures by adding hints * to the constraints.
Is it ok to commit?
2020-10-30 Vladimir Makarov <vmaka...@redhat.com>
* config/rs6000/vsx.md (*vsx_extract_<mode>_store_p9): Add
hints * to 1st scratch.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 67e4f2fd037..78de85ccbbb 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3717,7 +3717,7 @@
(vec_select:<VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>,v")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))
- (clobber (match_scratch:<VS_scalar> 3 "=<VSX_EX>,&r"))
+ (clobber (match_scratch:<VS_scalar> 3 "=*<VSX_EX>,&*r"))
(clobber (match_scratch:SI 4 "=X,&r"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
