On 9/16/20 4:00 PM, Dennis Zhang wrote: > Hi all, > > This patch enables SIMD modes for MVE auto-vectorization. > In this patch, the integer and float MVE SIMD modes are returned by > arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > MVE or MVE_FLOAT is enabled. > Then the expanders for auto-vectorization can be used for generating MVE > SIMD code. > > This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > revealed by the enabled MVE SIMD modes. > The tests are for checking the MVE reinterpret intrinsics. > There are two functions in each of the tests. The two functions contain > the pattern of identical code so that they are folded in icf pass. > Because of icf, the instruction count only checks one function which is 8. > However when the SIMD modes are enabled, the estimation of the code size > becomes smaller so that inlining is applied after icf, then the > instruction count becomes 16 which causes failure of the tests. > Because the icf is not the expected pattern to be tested but causes > above issues, -fno-ipa-icf is applied to the tests to avoid unstable > instruction count. > > This patch is separated from > https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > because this part is not strongly connected to the aim of that one so > that causing confusion. > > Regtested and bootstraped. > > Is it OK for trunk please? > > Thanks > Dennis > > gcc/ChangeLog: > > 2020-09-15 Dennis Zhang <dennis.zh...@arm.com> > > * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. > > gcc/testsuite/ChangeLog: > > 2020-09-15 Dennis Zhang <dennis.zh...@arm.com> > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional > option -fno-ipa-icf and change the instruction count from 8 to 16. > * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. >
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