On 9/24/20 10:59 AM, will schmidt via Gcc-patches wrote: > +;; Move DI value from GPR to TI mode in VSX register, word 1. > +(define_insn "mtvsrdd_diti_w1" > + [(set (match_operand:TI 0 "register_operand" "=wa") > + (unspec:TI [(match_operand:DI 1 "register_operand" "r")] > + UNSPEC_MTVSRD_DITI_W1))] > + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" > + "mtvsrdd %x0,0,%1" > + [(set_attr "type" "vecsimple")])
"vecmove" (since I just updated the other uses). > + > +;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg > +(define_insn "extendditi2_vector" > + [(set (match_operand:TI 0 "gpc_reg_operand" "=v") > + (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")] > + UNSPEC_EXTENDDITI2))] > + "TARGET_POWER10" > + "vextsd2q %0,%1" > + [(set_attr "type" "exts")]) "vecexts". > + > +(define_expand "extendditi2" > + [(set (match_operand:TI 0 "gpc_reg_operand") > + (sign_extend:DI (match_operand:DI 1 "gpc_reg_operand")))] > + "TARGET_POWER10" > + { > + /* Move 64-bit src from GPR to vector reg and sign extend to 128-bits */ > + rtx temp = gen_reg_rtx (TImode); > + emit_insn (gen_mtvsrdd_diti_w1 (temp, operands[1])); > + emit_insn (gen_extendditi2_vector (operands[0], temp)); > + DONE; > + } > + [(set_attr "type" "exts")]) Don't need "type" attr on define_expand since the type will come from the 2 individual insns emitted. Thanks, Pat