[PATCH][GCC 8] Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a

[Kyrylo Tkachov]

Hi all,

I'd like to backport this patch to the GCC 8 branch that implements intrinsics 
that were (erroneously) missed out
of the initial implementation in GCC 8.

Bootstrapped and tested on aarch64-none-linux-gnu on the branch.

This patch adds the missing neon intrinsics for all 128 bit vector Integer 
modes for the
three-way XOR and negate and xor instructions for Arm8.2-a to Armv8.4-a.

gcc/
2018-05-21  Tamar Christina  <tamar.christ...@arm.com>

        PR target/71233
        * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
        eor3q<mode>4.
        (aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
        * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
        veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
        vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
        vbcaxq_s64): New.
        * config/aarch64/arm_neon.h: Likewise.
        * config/aarch64/iterators.md (VQ_I): New.

gcc/testsuite/
2018-05-21  Tamar Christina  <tamar.christ...@arm.com>

        PR target/71233
        * gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32,
        veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
        vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
        vbcaxq_s64): New.
        * gcc.target/aarch64/sha3_1.c: Likewise.
        * gcc.target/aarch64/sha3_2.c: Likewise.
        * gcc.target/aarch64/sha3_3.c: Likewise.

(cherry picked from commit d21052ebd7ac9d545a26dde3229c57f872c1d5f3)

bcax.patch
Description: bcax.patch