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Hongyu Wang <wwwhhhyyy...@gmail.com> 于2020年8月4日周二 下午11:40写道： > > Kirill Yukhin <kirill.yuk...@gmail.com> 于2020年8月4日周二 下午10:47写道： > > > > Hello, > > > > On 06 июл 09:58, Hongyu Wang via Gcc-patches wrote: > > > Hi: > > > > > > This patch is about to support Intel Advanced Matrix Extensions (AMX) > > > which will be enabled in GLC. > > > > > > AMX is a new 64-bit programming paradigm consisting of two > > > compo nents: a set of 2-dimensional registers (tiles) representing > > > sub-arrays from a larger 2-dimensional memory image, > > > and an accelerator able to operate on tiles > > > > > > Supported instructions are > > > > > > AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease > > > AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud > > > AMX-BF16:tdpbf16ps > > > > > > The intrinsics adopts constant tile register number as its input > > > parameters. > > > > I didn't go into the patch deeply, but why did you use inline asm for > > intrinsics > > definition? Are you going to introduce register classes for thouse new tmm > > registers and new instruction definitions for new insns in machine > > description? > > In this version of patch, we just align our implementation to what > have been submitted > to llvm community. Since AMX allows variant register size in runtime > configuration, > the implementation of register allocation is still under discussion. > We will introduce > new register class and new insns in the future patch. > > > > > -- > > K
