Hi Omar, From: Omar Tahir <omar.ta...@arm.com> Sent: 04 August 2020 17:15 To: Kyrylo Tkachov <kyrylo.tkac...@arm.com>; ni...@redhat.com; Ramana Radhakrishnan <ramana.radhakrish...@arm.com>; Richard Earnshaw <richard.earns...@arm.com>; gcc-patches@gcc.gnu.org Subject: [PATCH 4/5][Arm] New pattern for CSNEG instructions
This patch adds a new pattern, *thumb2_csneg, for generating CSNEG instructions. It also restricts *if_neg_move and *thumb2_negscc to only match if !TARGET_COND_ARITH which prevents undesirable matches during ifcvt. Regression tested on arm-none-eabi. 2020-07-30: Sudakshina Das <mailto:sudi....@arm.com> Omar Tahir <mailto:omar.ta...@arm.com> * config/arm/thumb2.md (*thumb2_csneg): New. (*thumb2_negscc): Don't match if TARGET_COND_ARITH. * config/arm/arm.md (*if_neg_move): Don't match if TARGET_COND_ARITH. gcc/testsuite/ChangeLog: 2020-07-30: Sudakshina Das <mailto:sudi....@arm.com> Omar Tahir <mailto:omar.ta...@arm.com> * gcc.target/arm/csneg.c: New test. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a6a31f8f4ef..950e46edfee 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11211,7 +11211,7 @@ [(match_operand 3 "cc_register" "") (const_int 0)]) (neg:SI (match_operand:SI 2 "s_register_operand" "l,r")) (match_operand:SI 1 "s_register_operand" "0,0")))] - "TARGET_32BIT" + "TARGET_32BIT && !TARGET_COND_ARITH" "#" "&& reload_completed" [(cond_exec (match_op_dup 4 [(match_dup 3) (const_int 0)]) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 79cf684e5cb..d12467d7644 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -880,7 +880,7 @@ [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")]))) (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB2" + "TARGET_THUMB2 && !TARGET_COND_ARITH" "#" "&& reload_completed" [(const_int 0)] @@ -970,6 +970,20 @@ (set_attr "predicable" "no")] ) +(define_insn "*thumb2_csneg" + [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r") + (if_then_else:SI + (match_operand 1 "arm_comparison_operation" "") + (neg:SI (match_operand:SI 2 "arm_general_register_operand" "r, r")) + (match_operand:SI 3 "reg_or_zero_operand" "r, Z")))] + "TARGET_COND_ARITH" Minor nit, but please indent the pattern consistently with the other patterns in the file i.e. (if_then_else...) goes under the (match_operand:SI 0...) Same with the other patches in the series (sorry, I had missed that in the previous ones). Ok with that fix. Thanks, Kyrill + "@ + csneg\\t%0, %3, %2, %D1 + csneg\\t%0, zr, %2, %D1" + [(set_attr "type" "csel") + (set_attr "predicable" "no")] +) + (define_insn "*thumb2_movcond" [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts") (if_then_else:SI diff --git a/gcc/testsuite/gcc.target/arm/csneg.c b/gcc/testsuite/gcc.target/arm/csneg.c new file mode 100644 index 00000000000..e48606265af --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/csneg.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */ +/* { dg-options "-O2 -march=armv8.1-m.main" } */ + +int +test_csneg32_condasn1(int w0, int w1, int w2, int w3) +{ + int w4; + + /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*ne" } } */ + w4 = (w0 == w1) ? -w2 : w3; + return w4; +} + +int +test_csneg32_condasn2(int w0, int w1, int w2, int w3) +{ + int w4; + + /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*eq" } } */ + w4 = (w0 == w1) ? w3 : -w2; + return w4; +} + +unsigned long long +test_csneg_uxtw (unsigned int a, unsigned int b, unsigned int c) +{ + unsigned int val; + + /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*ne" } } */ + val = a ? b : -c; + return val; +}
