On Thu, Aug 06, 2020 at 10:31:27AM +0200, Richard Biener wrote:
> > For x86, for example, even though the GPR registers are 64-bit, we only 
> > need to zero the lower 32-bit. etc.
> 
> That's an optimization, yes.

But, does the code need to care?
If one compiles:
void
foo ()
{
  register unsigned long long a __asm ("rax");
  register unsigned long long b __asm ("rsi");
  register unsigned long long c __asm ("r8");
  register unsigned long long d __asm ("r9");
  a = 0;
  b = 0;
  c = 0;
  d = 0;
  asm volatile ("" : : "r" (a), "r" (b), "r" (c), "r" (d));
}
then the backend uses *movdi_xor patterns which are emitted
as xorl instructions (i.e. just 32-bit).  If you need to emit them
at a spot where the flags register is or might be live, then
*movdi_internal is used instead, but that one will also emit
a 32-bit movl $0, %r8d etc. instruction (because (const_int 0) is
zero extended 32-bit integer).

        Jakub

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