Richard, In attachment reworked patch. > -----Original Message----- > From: Richard Sandiford <richard.sandif...@arm.com> > Sent: 13 July 2020 17:13 > To: Przemyslaw Wirkus <przemyslaw.wir...@arm.com> > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw > <richard.earns...@arm.com>; Marcus Shawcroft > <marcus.shawcr...@arm.com>; Kyrylo Tkachov <kyrylo.tkac...@arm.com> > Subject: Re: [PATCH][GCC][aarch64] Generation of adjusted ldp/stp for vector > types > > Hi, > > Sorry for the slow review.
Thank you for all your comments. They were insightful. I've simplified my patch to match them. > Przemyslaw Wirkus <przemyslaw.wir...@arm.com> writes: > > Hi, > > > > Introduce simple peephole2 optimization which substitutes a sequence > > of four consecutive load or store (LDR, STR) instructions with two > > load or store pair (LDP, STP) instructions for 2 element supported > > vector modes (V2SI, V2SF, V2DI, and V2DF). > > Generated load / store pair instruction offset is adjusted accordingly. [snip...] Kind regards, Przemyslaw Wirkus
rb13293.patch
Description: rb13293.patch
