Hi!
On Wed, Jul 08, 2020 at 11:19:21AM +0800, luoxhu wrote:
> For extracting high part element from DImode register like:
>
> {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
>
> split it before reload with "and mask" to avoid generating shift right
> 32 bit then shift left 32 bit. This pattern also exists in PR42475 and
> PR67741, etc.
> 2020-07-08 Xionghu Luo <luo...@linux.ibm.com>
>
> PR rtl-optimization/89310
> * config/rs6000/rs6000.md (movsf_from_si2): New
> define_insn_and_split.
>
> gcc/testsuite/ChangeLog:
>
> 2020-07-08 Xionghu Luo <luo...@linux.ibm.com>
>
> PR rtl-optimization/89310
> * gcc.target/powerpc/pr89310.c: New test.
> +;; For extracting high part element from DImode register like:
> +;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}
> +;; split it before reload with "and mask" to avoid generating shift right
> +;; 32 bit then shift left 32 bit.
> +(define_insn_and_split "movsf_from_si2"
> + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
> + (unspec:SF [
> + (subreg:SI (ashiftrt:DI
Put the (ashiftrt:DI on a separate line as well? With indent changes,
etc.
> + (match_operand:DI 1 "input_operand" "r")
> + (const_int 32))
> + 0)]
> + UNSPEC_SF_FROM_SI))
> + (clobber (match_scratch:DI 2 "=r"))]
> + "TARGET_NO_SF_SUBREG"
> + "@
> + #"
@ with only one alternative doesn't do anything; so just write
"#"
please.
> +
And no empty line here.
> + "&& !reload_completed
Why this? Why will this not work after reload? In the very few cases
where you do need this, you usually also need to check for
lra_in_progress.
> + && vsx_reg_sfsubreg_ok (operands[0], SFmode)"
> + [(const_int 0)]
> +{
> + if (GET_CODE (operands[2]) == SCRATCH)
> + operands[2] = gen_reg_rtx (DImode);
> +
> + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << 32);
The mask should be different for QI and HI.
> + emit_insn (gen_anddi3 (operands[2], operands[1], mask));
> + emit_insn (gen_p8_mtvsrd_sf (operands[0], operands[2]));
> + emit_insn (gen_vsx_xscvspdpn_directmove (operands[0], operands[0]));
> + DONE;
> +}
> + [(set_attr "length" "12")
> + (set_attr "type" "vecfloat")
> + (set_attr "isa" "p8v")])
> +
No extra whiteline please.
Maybe change it back to just SI? It won't match often at all for QI or
HI anyway, it seems. Sorry for that detour. Should be good with the
above nits fixed :-)
Segher
