After Thumb-2's peephole2 adds flag clobbering on suitable insns in order to generate 16-bit encoding for them, if-conversion can't transform these insns into cond_execs. In theory, if the instruction were converted to conditional form, it would also use 16-bit encoding, so the flag clobbering doesn't have to be added to force 16-bit encoding. Swapping order of these passes has actually increased the number of if-conversions (it results in 2% more it-blocks on SPEC2K INT and 4% more "long" it-blocks that contain two or more instructions). However, this actually caused 2038 code size regression on SPEC2K INT. At first, we blamed this growth on the effects described in patches 1-4, but with these fixes the regression has only reduced by 474 bytes. I.e. the more there are conditional insns, the better is the code size reduction from patches 1-4, but altered pass order still loses 1564 bytes to the original one.
What do you think about the order of these passes on Thumb-2?

(The patch is obvious, and is not attached).

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