> -----Original Message-----
> From: Gcc-patches <gcc-patches-boun...@gcc.gnu.org> On Behalf Of Alex
> Coplan
> Sent: 18 May 2020 16:37
> To: Kyrylo Tkachov <kyrylo.tkac...@arm.com>; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw <richard.earns...@arm.com>; nd <n...@arm.com>; Ramana
> Radhakrishnan <ramana.radhakrish...@arm.com>
> Subject: RE: [PATCH] [arm] Don't generate invalid LDRD insns
>
> > -----Original Message-----
> > From: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
> > Sent: 15 May 2020 11:57
> > To: Alex Coplan <alex.cop...@arm.com>; gcc-patches@gcc.gnu.org
> > Cc: nd <n...@arm.com>; ni...@redhat.com; Richard Earnshaw
> > <richard.earns...@arm.com>; Ramana Radhakrishnan
> <ramana.radhakrish...@arm.com>
> > Subject: RE: [PATCH] [arm] Don't generate invalid LDRD insns
> >
> > Hi Alex,
> >
> > > -----Original Message-----
> > > From: Alex Coplan <alex.cop...@arm.com>
> > > Sent: 15 May 2020 11:36
> > > To: gcc-patches@gcc.gnu.org
> > > Cc: nd <n...@arm.com>; ni...@redhat.com; Richard Earnshaw
> > > <richard.earns...@arm.com>; Ramana Radhakrishnan
> > > <ramana.radhakrish...@arm.com>; Kyrylo Tkachov
> > > <kyrylo.tkac...@arm.com>
> > > Subject: [PATCH] [arm] Don't generate invalid LDRD insns
> > >
> > > Hello,
> > >
> > > This patch fixes a bug in the arm backend where GCC generates invalid
> LDRD
> > > instructions. The LDRD instruction requires the first transfer
> register to be
> > > even, but GCC attempts to use odd registers here. For example, with
> the
> > > following C code:
> > >
> > > struct c {
> > > double a;
> > > } __attribute((aligned)) __attribute((packed));
> > > struct c d;
> > > struct c f(struct c);
> > > void e() { f(d); }
> > >
> > > The struct d is passed in registers r1 and r2 to the function f, and
> GCC
> > > attempts to do this with a LDRD instruction when compiling with -
> > > march=armv7-a
> > > on a soft float toolchain.
> > >
> > > The fix is analogous to the corresponding one for STRD in the same
> function:
> > >
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=52057dc4ac5295caebf83147f6
> > > 88d769c93cbc8d
> > >
> > > Testing:
> > > - New unit tests which pass after applying the patch.
> > > - Tested on an x64 -> arm-none-eabi cross.
> > > - Bootstrapped and regtested on arm-none-linux-gnueabihf (in both
> thumb
> > > and arm
> > > modes).
> > >
> > > OK for master?
> >
> > Ok.
> > Please apply for write-after-approval commit access to the repo by
> filling the
> > form at:
> > https://sourceware.org/cgi-bin/pdw/ps_form.cgi
> > listing me as your sponsor.
> > You can then push the patch yourself.
>
> OK, I've pushed the patch to master.
>
> Thanks,
> Alex
This patch applies cleanly on gcc-{8,9,10} branches. I've run bootstrap
and regression tests (both thumb and arm) with the patch applied to the
branches and those came back clean.
OK to backport to the branches?
Thanks,
Alex
>
> >
> > Thanks,
> > Kyrill
> >
> > >
> > > Thanks,
> > > Alex
> > >
> > > ---
> > >
> > > gcc/ChangeLog:
> > >
> > > 2020-05-15 Alex Coplan <alex.cop...@arm.com>
> > > * config/arm/arm.c (output_move_double): Fix codegen when
> loading
> > > into
> > > a register pair with an odd base register.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > 2020-05-15 Alex Coplan <alex.cop...@arm.com>
> > > * gcc.c-torture/compile/packed-aligned-1.c: New test.
> > > * gcc.c-torture/execute/packed-aligned.c: New test.
> >
