On Wed, Jun 24, 2020 at 12:31 AM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> [CC list removed, it is not shown in archives]
>
> > In i386-builtins.c, arch_names_table is used to to map architecture name
> > string to internal model. A switch statement is used to map internal
> > processor name to architecture name string and internal priority.
> >
> > model and priority are added to processor_alias_table so that a single
> > entry contains architecture name string, internal processor name,
> > internal model and internal priority. 6 entries are appended for
> > i386-builtins.c, which have special architecture name strings: amd,
> > amdfam10h, amdfam15h, amdfam17h, shanghai and istanbul, and pta_size is
> > adjusted to exclude them. Entries which are not used by i386-builtins.c
>
> We already have an "amdfam10" entry, so I think these should later be
> extended by AMD folks to include correct processor_type, schedule
> model and flags. Having to manually exclude generic entries feels a
> bit hackish, though, but the patch is certainly an improvement.
>
> > have internal model 0. P_PROC_DYNAMIC is added to internal priority to
> > make entries with dynamic architecture name string or priority.
>
> BTW: Can you please change P_ZERO to P_NONE?
Fixed.
> > PR target/95842
> > * common/config/i386/i386-common.c (processor_alias_table): Add
> > processor model and priority to each entry.
> > (pta_size): Updated with -6.
> > (num_arch_names): New.
> > * common/config/i386/i386-cpuinfo.h: New file.
> > * config/i386/i386-builtins.c (feature_priority): Removed.
> > (processor_model): Likewise.
> > (_arch_names_table): Likewise.
> > (arch_names_table): Likewise.
> > (get_builtin_code_for_version): Use processor_alias_table.
> > (fold_builtin_cpu): Replace arch_names_table with
> > processor_alias_table.
> > * config/i386/i386.h: Include "common/config/i386/i386-cpuinfo.h".
> > (pta): Add model and priority.
> > (num_arch_names): New.
>
> LGTM.
>
> Thanks,
> Uros.
This is the patch I am checking in.
Thanks.
--
H.J.
From e4d03220e495f8b316d088b49a9143a13b8180d4 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.to...@gmail.com>
Date: Tue, 23 Jun 2020 12:49:32 -0700
Subject: [PATCH] x86: Fold arch_names_table into processor_alias_table
In i386-builtins.c, arch_names_table is used to to map architecture name
string to internal model. A switch statement is used to map internal
processor name to architecture name string and internal priority.
model and priority are added to processor_alias_table so that a single
entry contains architecture name string, internal processor name,
internal model and internal priority. 6 entries are appended for
i386-builtins.c, which have special architecture name strings: amd,
amdfam10h, amdfam15h, amdfam17h, shanghai and istanbul, and pta_size is
adjusted to exclude them. Entries which are not used by i386-builtins.c
have internal model 0. P_PROC_DYNAMIC is added to internal priority to
make entries with dynamic architecture name string or priority.
PR target/95842
* common/config/i386/i386-common.c (processor_alias_table): Add
processor model and priority to each entry.
(pta_size): Updated with -6.
(num_arch_names): New.
* common/config/i386/i386-cpuinfo.h: New file.
* config/i386/i386-builtins.c (feature_priority): Removed.
(processor_model): Likewise.
(_arch_names_table): Likewise.
(arch_names_table): Likewise.
(_isa_names_table): Replace P_ZERO with P_NONE.
(get_builtin_code_for_version): Replace P_ZERO with P_NONE. Use
processor_alias_table.
(fold_builtin_cpu): Replace arch_names_table with
processor_alias_table.
* config/i386/i386.h: Include "common/config/i386/i386-cpuinfo.h".
(pta): Add model and priority.
(num_arch_names): New.
---
gcc/common/config/i386/i386-common.c | 239 ++++++++++-------
gcc/common/config/i386/i386-cpuinfo.h | 134 ++++++++++
gcc/config/i386/i386-builtins.c | 371 ++++++--------------------
gcc/config/i386/i386.h | 5 +
4 files changed, 366 insertions(+), 383 deletions(-)
create mode 100644 gcc/common/config/i386/i386-cpuinfo.h
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 42d14c29f16..654df68d688 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1619,164 +1619,202 @@ STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
const pta processor_alias_table[] =
{
- {"i386", PROCESSOR_I386, CPU_NONE, 0},
- {"i486", PROCESSOR_I486, CPU_NONE, 0},
- {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
- {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
- {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
- {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+ {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
+ {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
+ {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
+ {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
+ {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
+ 0, P_NONE},
+ {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
+ {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
+ {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
+ 0, P_NONE},
+ {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
+ {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
+ 0, P_NONE},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
{"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
- {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
+ {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
+ {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
+ {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
+ 0, P_NONE},
{"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
{"prescott", PROCESSOR_NOCONA, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
{"nocona", PROCESSOR_NOCONA, CPU_NONE,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
- {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
- {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+ | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
+ {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
+ M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
+ {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
+ M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
+ {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
+ M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
+ {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
+ M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
{"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ PTA_SANDYBRIDGE,
+ M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
{"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
{"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
+ PTA_IVYBRIDGE,
+ M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
{"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
- {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
- {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
+ PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
+ {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
+ M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
+ {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
+ 0, P_PROC_DYNAMIC},
+ {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
+ M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
+ {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
- PTA_SKYLAKE_AVX512},
- {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
+ PTA_SKYLAKE_AVX512,
+ M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
+ {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
{"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
- PTA_ICELAKE_CLIENT},
+ PTA_ICELAKE_CLIENT,
+ M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
{"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
- PTA_ICELAKE_SERVER},
+ PTA_ICELAKE_SERVER,
+ M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
{"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
- PTA_CASCADELAKE},
- {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE},
- {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE},
- {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
- {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
- {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
- {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
- {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
- {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+ PTA_CASCADELAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
+ {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
+ {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
+ {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
+ M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
+ {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
+ M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
+ {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
+ M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
+ {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
+ M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
+ {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
+ M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
+ {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
+ M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
+ {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT,
+ M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
+ {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL,
+ M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F},
+ {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM,
+ M_CPU_TYPE (INTEL_KNM), P_PROC_AVX512F},
+ {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM,
+ M_VENDOR (VENDOR_INTEL), P_NONE},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
- {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
- {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
- {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
+ {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
+ {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
+ {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
{"x86-64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR,
+ 0, P_NONE},
{"eden-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
+ 0, P_NONE},
{"nano", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
{"nano-1000", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
{"nano-2000", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
{"nano-3000", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"nano-x2", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"eden-x4", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"nano-x4", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"opteron", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"athlon64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
+ 0, P_PROC_DYNAMIC},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
+ M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
+ M_CPU_TYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
+ M_CPU_TYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT | PTA_FSGSBASE},
+ | PTA_XSAVEOPT | PTA_FSGSBASE,
+ M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -1784,7 +1822,8 @@ const pta processor_alias_table[] =
| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
- | PTA_MOVBE | PTA_MWAITX},
+ | PTA_MOVBE | PTA_MWAITX,
+ M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
{"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -1793,7 +1832,8 @@ const pta processor_alias_table[] =
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
- | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+ | PTA_SHA | PTA_LZCNT | PTA_POPCNT,
+ M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
{"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -1803,24 +1843,43 @@ const pta processor_alias_table[] =
| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
| PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
- | PTA_WBNOINVD},
+ | PTA_WBNOINVD,
+ M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE},
+ | PTA_FXSR | PTA_XSAVE,
+ M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_SSE4_A},
{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+ | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT,
+ M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
PTA_64BIT
- | PTA_HLE /* flags are only used for -march switch. */ },
+ | PTA_HLE /* flags are only used for -march switch. */,
+ 0, P_NONE},
+
+ {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_VENDOR (VENDOR_AMD), P_NONE},
+ {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM10H), P_NONE},
+ {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM15H), P_NONE},
+ {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM17H), P_NONE},
+ {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM10H_SHANGHAI), P_NONE},
+ {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+ M_CPU_TYPE (AMDFAM10H_ISTANBUL), P_NONE},
};
-int const pta_size = ARRAY_SIZE (processor_alias_table);
+/* NB: processor_alias_table stops at the "generic" entry. */
+int const pta_size = ARRAY_SIZE (processor_alias_table) - 6;
+unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
/* Provide valid option values for -march and -mtune options. */
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
new file mode 100644
index 00000000000..e11c68f46dd
--- /dev/null
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -0,0 +1,134 @@
+/* Get CPU type and Features for x86 processors.
+ Copyright (C) 2012-2020 Free Software Foundation, Inc.
+ Contributed by Sriraman Tallam (tmsri...@google.com)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+<http://www.gnu.org/licenses/>. */
+
+/* Processor Vendor and Models. */
+
+enum processor_vendor
+{
+ VENDOR_INTEL = 1,
+ VENDOR_AMD,
+ VENDOR_OTHER,
+ BUILTIN_VENDOR_MAX = VENDOR_OTHER,
+ VENDOR_MAX
+};
+
+/* Any new types or subtypes have to be inserted at the end. */
+
+enum processor_types
+{
+ INTEL_BONNELL = 1,
+ INTEL_CORE2,
+ INTEL_COREI7,
+ AMDFAM10H,
+ AMDFAM15H,
+ INTEL_SILVERMONT,
+ INTEL_KNL,
+ AMD_BTVER1,
+ AMD_BTVER2,
+ AMDFAM17H,
+ INTEL_KNM,
+ INTEL_GOLDMONT,
+ INTEL_GOLDMONT_PLUS,
+ INTEL_TREMONT,
+ CPU_TYPE_MAX,
+ BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
+};
+
+enum processor_subtypes
+{
+ INTEL_COREI7_NEHALEM = 1,
+ INTEL_COREI7_WESTMERE,
+ INTEL_COREI7_SANDYBRIDGE,
+ AMDFAM10H_BARCELONA,
+ AMDFAM10H_SHANGHAI,
+ AMDFAM10H_ISTANBUL,
+ AMDFAM15H_BDVER1,
+ AMDFAM15H_BDVER2,
+ AMDFAM15H_BDVER3,
+ AMDFAM15H_BDVER4,
+ AMDFAM17H_ZNVER1,
+ INTEL_COREI7_IVYBRIDGE,
+ INTEL_COREI7_HASWELL,
+ INTEL_COREI7_BROADWELL,
+ INTEL_COREI7_SKYLAKE,
+ INTEL_COREI7_SKYLAKE_AVX512,
+ INTEL_COREI7_CANNONLAKE,
+ INTEL_COREI7_ICELAKE_CLIENT,
+ INTEL_COREI7_ICELAKE_SERVER,
+ AMDFAM17H_ZNVER2,
+ INTEL_COREI7_CASCADELAKE,
+ INTEL_COREI7_TIGERLAKE,
+ INTEL_COREI7_COOPERLAKE,
+ CPU_SUBTYPE_MAX
+};
+
+/* Priority of i386 features, greater value is higher priority. This is
+ used to decide the order in which function dispatch must happen. For
+ instance, a version specialized for SSE4.2 should be checked for dispatch
+ before a version for SSE3, as SSE4.2 implies SSE3. */
+enum feature_priority
+{
+ P_NONE = 0,
+ P_MMX,
+ P_SSE,
+ P_SSE2,
+ P_SSE3,
+ P_SSSE3,
+ P_PROC_SSSE3,
+ P_SSE4_A,
+ P_PROC_SSE4_A,
+ P_SSE4_1,
+ P_SSE4_2,
+ P_PROC_SSE4_2,
+ P_POPCNT,
+ P_AES,
+ P_PCLMUL,
+ P_AVX,
+ P_PROC_AVX,
+ P_BMI,
+ P_PROC_BMI,
+ P_FMA4,
+ P_XOP,
+ P_PROC_XOP,
+ P_FMA,
+ P_PROC_FMA,
+ P_BMI2,
+ P_AVX2,
+ P_PROC_AVX2,
+ P_AVX512F,
+ P_PROC_AVX512F,
+ P_PROC_DYNAMIC
+};
+
+/* These are the values for vendor types, cpu types and subtypes. Cpu
+ types and subtypes should be subtracted by the corresponding start
+ value. */
+
+#define M_CPU_TYPE_START (BUILTIN_VENDOR_MAX)
+#define M_CPU_SUBTYPE_START \
+ (M_CPU_TYPE_START + BUILTIN_CPU_TYPE_MAX)
+#define M_VENDOR(a) (a)
+#define M_CPU_TYPE(a) (M_CPU_TYPE_START + a)
+#define M_CPU_SUBTYPE(a) (M_CPU_SUBTYPE_START + a)
diff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-builtins.c
index be3ed0158f2..6f6a8328ef1 100644
--- a/gcc/config/i386/i386-builtins.c
+++ b/gcc/config/i386/i386-builtins.c
@@ -1835,43 +1835,6 @@ ix86_builtin_reciprocal (tree fndecl)
}
}
-/* Priority of i386 features, greater value is higher priority. This is
- used to decide the order in which function dispatch must happen. For
- instance, a version specialized for SSE4.2 should be checked for dispatch
- before a version for SSE3, as SSE4.2 implies SSE3. */
-enum feature_priority
-{
- P_ZERO = 0,
- P_MMX,
- P_SSE,
- P_SSE2,
- P_SSE3,
- P_SSSE3,
- P_PROC_SSSE3,
- P_SSE4_A,
- P_PROC_SSE4_A,
- P_SSE4_1,
- P_SSE4_2,
- P_PROC_SSE4_2,
- P_POPCNT,
- P_AES,
- P_PCLMUL,
- P_AVX,
- P_PROC_AVX,
- P_BMI,
- P_PROC_BMI,
- P_FMA4,
- P_XOP,
- P_PROC_XOP,
- P_FMA,
- P_PROC_FMA,
- P_BMI2,
- P_AVX2,
- P_PROC_AVX2,
- P_AVX512F,
- P_PROC_AVX512F
-};
-
/* This is the order of bit-fields in __processor_features in cpuinfo.c */
enum processor_features
{
@@ -1916,105 +1879,6 @@ enum processor_features
F_MAX
};
-/* These are the values for vendor types and cpu types and subtypes
- in cpuinfo.c. Cpu types and subtypes should be subtracted by
- the corresponding start value. */
-enum processor_model
-{
- M_INTEL = 1,
- M_AMD,
- M_CPU_TYPE_START,
- M_INTEL_BONNELL,
- M_INTEL_CORE2,
- M_INTEL_COREI7,
- M_AMDFAM10H,
- M_AMDFAM15H,
- M_INTEL_SILVERMONT,
- M_INTEL_KNL,
- M_AMD_BTVER1,
- M_AMD_BTVER2,
- M_AMDFAM17H,
- M_INTEL_KNM,
- M_INTEL_GOLDMONT,
- M_INTEL_GOLDMONT_PLUS,
- M_INTEL_TREMONT,
- M_CPU_SUBTYPE_START,
- M_INTEL_COREI7_NEHALEM,
- M_INTEL_COREI7_WESTMERE,
- M_INTEL_COREI7_SANDYBRIDGE,
- M_AMDFAM10H_BARCELONA,
- M_AMDFAM10H_SHANGHAI,
- M_AMDFAM10H_ISTANBUL,
- M_AMDFAM15H_BDVER1,
- M_AMDFAM15H_BDVER2,
- M_AMDFAM15H_BDVER3,
- M_AMDFAM15H_BDVER4,
- M_AMDFAM17H_ZNVER1,
- M_INTEL_COREI7_IVYBRIDGE,
- M_INTEL_COREI7_HASWELL,
- M_INTEL_COREI7_BROADWELL,
- M_INTEL_COREI7_SKYLAKE,
- M_INTEL_COREI7_SKYLAKE_AVX512,
- M_INTEL_COREI7_CANNONLAKE,
- M_INTEL_COREI7_ICELAKE_CLIENT,
- M_INTEL_COREI7_ICELAKE_SERVER,
- M_AMDFAM17H_ZNVER2,
- M_INTEL_COREI7_CASCADELAKE,
- M_INTEL_COREI7_TIGERLAKE,
- M_INTEL_COREI7_COOPERLAKE
-};
-
-struct _arch_names_table
-{
- const char *const name;
- const enum processor_model model;
-};
-
-static const _arch_names_table arch_names_table[] =
-{
- {"amd", M_AMD},
- {"intel", M_INTEL},
- {"atom", M_INTEL_BONNELL},
- {"slm", M_INTEL_SILVERMONT},
- {"core2", M_INTEL_CORE2},
- {"corei7", M_INTEL_COREI7},
- {"nehalem", M_INTEL_COREI7_NEHALEM},
- {"westmere", M_INTEL_COREI7_WESTMERE},
- {"sandybridge", M_INTEL_COREI7_SANDYBRIDGE},
- {"ivybridge", M_INTEL_COREI7_IVYBRIDGE},
- {"haswell", M_INTEL_COREI7_HASWELL},
- {"broadwell", M_INTEL_COREI7_BROADWELL},
- {"skylake", M_INTEL_COREI7_SKYLAKE},
- {"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
- {"cannonlake", M_INTEL_COREI7_CANNONLAKE},
- {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
- {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
- {"cascadelake", M_INTEL_COREI7_CASCADELAKE},
- {"tigerlake", M_INTEL_COREI7_TIGERLAKE},
- {"cooperlake", M_INTEL_COREI7_COOPERLAKE},
- {"bonnell", M_INTEL_BONNELL},
- {"silvermont", M_INTEL_SILVERMONT},
- {"goldmont", M_INTEL_GOLDMONT},
- {"goldmont-plus", M_INTEL_GOLDMONT_PLUS},
- {"tremont", M_INTEL_TREMONT},
- {"knl", M_INTEL_KNL},
- {"knm", M_INTEL_KNM},
- {"amdfam10h", M_AMDFAM10H},
- {"barcelona", M_AMDFAM10H_BARCELONA},
- {"shanghai", M_AMDFAM10H_SHANGHAI},
- {"istanbul", M_AMDFAM10H_ISTANBUL},
- {"btver1", M_AMD_BTVER1},
- {"amdfam15h", M_AMDFAM15H},
- {"bdver1", M_AMDFAM15H_BDVER1},
- {"bdver2", M_AMDFAM15H_BDVER2},
- {"bdver3", M_AMDFAM15H_BDVER3},
- {"bdver4", M_AMDFAM15H_BDVER4},
- {"btver2", M_AMD_BTVER2},
- {"amdfam17h", M_AMDFAM17H},
- {"znver1", M_AMDFAM17H_ZNVER1},
- {"znver2", M_AMDFAM17H_ZNVER2},
-};
-
/* These are the target attribute strings for which a dispatcher is
available, from fold_builtin_cpu. */
struct _isa_names_table
@@ -2026,7 +1890,7 @@ struct _isa_names_table
static const _isa_names_table isa_names_table[] =
{
- {"cmov", F_CMOV, P_ZERO},
+ {"cmov", F_CMOV, P_NONE},
{"mmx", F_MMX, P_MMX},
{"popcnt", F_POPCNT, P_POPCNT},
{"sse", F_SSE, P_SSE},
@@ -2046,24 +1910,24 @@ static const _isa_names_table isa_names_table[] =
{"bmi2", F_BMI2, P_BMI2},
{"aes", F_AES, P_AES},
{"pclmul", F_PCLMUL, P_PCLMUL},
- {"avx512vl",F_AVX512VL, P_ZERO},
- {"avx512bw",F_AVX512BW, P_ZERO},
- {"avx512dq",F_AVX512DQ, P_ZERO},
- {"avx512cd",F_AVX512CD, P_ZERO},
- {"avx512er",F_AVX512ER, P_ZERO},
- {"avx512pf",F_AVX512PF, P_ZERO},
- {"avx512vbmi",F_AVX512VBMI, P_ZERO},
- {"avx512ifma",F_AVX512IFMA, P_ZERO},
- {"avx5124vnniw",F_AVX5124VNNIW, P_ZERO},
- {"avx5124fmaps",F_AVX5124FMAPS, P_ZERO},
- {"avx512vpopcntdq",F_AVX512VPOPCNTDQ, P_ZERO},
- {"avx512vbmi2", F_AVX512VBMI2, P_ZERO},
- {"gfni", F_GFNI, P_ZERO},
- {"vpclmulqdq", F_VPCLMULQDQ, P_ZERO},
- {"avx512vnni", F_AVX512VNNI, P_ZERO},
- {"avx512bitalg", F_AVX512BITALG, P_ZERO},
- {"avx512bf16", F_AVX512BF16, P_ZERO},
- {"avx512vp2intersect",F_AVX512VP2INTERSECT, P_ZERO}
+ {"avx512vl",F_AVX512VL, P_NONE},
+ {"avx512bw",F_AVX512BW, P_NONE},
+ {"avx512dq",F_AVX512DQ, P_NONE},
+ {"avx512cd",F_AVX512CD, P_NONE},
+ {"avx512er",F_AVX512ER, P_NONE},
+ {"avx512pf",F_AVX512PF, P_NONE},
+ {"avx512vbmi",F_AVX512VBMI, P_NONE},
+ {"avx512ifma",F_AVX512IFMA, P_NONE},
+ {"avx5124vnniw",F_AVX5124VNNIW, P_NONE},
+ {"avx5124fmaps",F_AVX5124FMAPS, P_NONE},
+ {"avx512vpopcntdq",F_AVX512VPOPCNTDQ, P_NONE},
+ {"avx512vbmi2", F_AVX512VBMI2, P_NONE},
+ {"gfni", F_GFNI, P_NONE},
+ {"vpclmulqdq", F_VPCLMULQDQ, P_NONE},
+ {"avx512vnni", F_AVX512VNNI, P_NONE},
+ {"avx512bitalg", F_AVX512BITALG, P_NONE},
+ {"avx512bf16", F_AVX512BF16, P_NONE},
+ {"avx512vp2intersect",F_AVX512VP2INTERSECT, P_NONE}
};
/* This parses the attribute arguments to target in DECL and determines
@@ -2084,7 +1948,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
char *tok_str = NULL;
char *token;
- enum feature_priority priority = P_ZERO;
+ enum feature_priority priority = P_NONE;
static unsigned int NUM_FEATURES
= sizeof (isa_names_table) / sizeof (_isa_names_table);
@@ -2125,140 +1989,62 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
gcc_assert (new_target);
if (new_target->arch_specified && new_target->arch > 0)
- {
- switch (new_target->arch)
+ for (i = 0; i < (unsigned int) pta_size; i++)
+ if (processor_alias_table[i].processor == new_target->arch)
{
- case PROCESSOR_CORE2:
- arg_str = "core2";
- priority = P_PROC_SSSE3;
- break;
- case PROCESSOR_NEHALEM:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_PCLMUL)
+ const pta *arch_info = &processor_alias_table[i];
+ switch (arch_info->priority)
{
- arg_str = "westmere";
- priority = P_PCLMUL;
+ default:
+ arg_str = arch_info->name;
+ priority = arch_info->priority;
+ break;
+ case P_PROC_DYNAMIC:
+ switch (new_target->arch)
+ {
+ case PROCESSOR_NEHALEM:
+ if (TARGET_PCLMUL_P (new_target->x_ix86_isa_flags))
+ {
+ arg_str = "westmere";
+ priority = P_PCLMUL;
+ }
+ else
+ {
+ /* We translate "arch=corei7" and "arch=nehalem"
+ to "corei7" so that it will be mapped to
+ M_INTEL_COREI7 as cpu type to cover all
+ M_INTEL_COREI7_XXXs. */
+ arg_str = "corei7";
+ priority = P_PROC_SSE4_2;
+ }
+ break;
+ case PROCESSOR_SANDYBRIDGE:
+ if (TARGET_F16C_P (new_target->x_ix86_isa_flags))
+ arg_str = "ivybridge";
+ else
+ arg_str = "sandybridge";
+ priority = P_PROC_AVX;
+ break;
+ case PROCESSOR_HASWELL:
+ if (TARGET_ADX_P (new_target->x_ix86_isa_flags))
+ arg_str = "broadwell";
+ else
+ arg_str = "haswell";
+ priority = P_PROC_AVX2;
+ break;
+ case PROCESSOR_AMDFAM10:
+ arg_str = "amdfam10h";
+ priority = P_PROC_SSE4_A;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ case P_NONE:
+ break;
}
- else
- {
- /* We translate "arch=corei7" and "arch=nehalem" to
- "corei7" so that it will be mapped to M_INTEL_COREI7
- as cpu type to cover all M_INTEL_COREI7_XXXs. */
- arg_str = "corei7";
- priority = P_PROC_SSE4_2;
- }
- break;
- case PROCESSOR_SANDYBRIDGE:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_F16C)
- arg_str = "ivybridge";
- else
- arg_str = "sandybridge";
- priority = P_PROC_AVX;
- break;
- case PROCESSOR_HASWELL:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_ADX)
- arg_str = "broadwell";
- else
- arg_str = "haswell";
- priority = P_PROC_AVX2;
- break;
- case PROCESSOR_SKYLAKE:
- arg_str = "skylake";
- priority = P_PROC_AVX2;
- break;
- case PROCESSOR_SKYLAKE_AVX512:
- arg_str = "skylake-avx512";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_CANNONLAKE:
- arg_str = "cannonlake";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_ICELAKE_CLIENT:
- arg_str = "icelake-client";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_ICELAKE_SERVER:
- arg_str = "icelake-server";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_CASCADELAKE:
- arg_str = "cascadelake";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_TIGERLAKE:
- arg_str = "tigerlake";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_COOPERLAKE:
- arg_str = "cooperlake";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_BONNELL:
- arg_str = "bonnell";
- priority = P_PROC_SSSE3;
- break;
- case PROCESSOR_KNL:
- arg_str = "knl";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_KNM:
- arg_str = "knm";
- priority = P_PROC_AVX512F;
- break;
- case PROCESSOR_SILVERMONT:
- arg_str = "silvermont";
- priority = P_PROC_SSE4_2;
- break;
- case PROCESSOR_GOLDMONT:
- arg_str = "goldmont";
- priority = P_PROC_SSE4_2;
- break;
- case PROCESSOR_GOLDMONT_PLUS:
- arg_str = "goldmont-plus";
- priority = P_PROC_SSE4_2;
- break;
- case PROCESSOR_TREMONT:
- arg_str = "tremont";
- priority = P_PROC_SSE4_2;
- break;
- case PROCESSOR_AMDFAM10:
- arg_str = "amdfam10h";
- priority = P_PROC_SSE4_A;
- break;
- case PROCESSOR_BTVER1:
- arg_str = "btver1";
- priority = P_PROC_SSE4_A;
- break;
- case PROCESSOR_BTVER2:
- arg_str = "btver2";
- priority = P_PROC_BMI;
- break;
- case PROCESSOR_BDVER1:
- arg_str = "bdver1";
- priority = P_PROC_XOP;
- break;
- case PROCESSOR_BDVER2:
- arg_str = "bdver2";
- priority = P_PROC_FMA;
- break;
- case PROCESSOR_BDVER3:
- arg_str = "bdver3";
- priority = P_PROC_FMA;
- break;
- case PROCESSOR_BDVER4:
- arg_str = "bdver4";
- priority = P_PROC_AVX2;
- break;
- case PROCESSOR_ZNVER1:
- arg_str = "znver1";
- priority = P_PROC_AVX2;
- break;
- case PROCESSOR_ZNVER2:
- arg_str = "znver2";
- priority = P_PROC_AVX2;
break;
}
- }
cl_target_option_restore (&global_options, &cur_target);
@@ -2312,7 +2098,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
break;
}
}
- if (predicate_list && priority == P_ZERO)
+ if (predicate_list && priority == P_NONE)
{
error_at (DECL_SOURCE_LOCATION (decl),
"ISA %qs is not supported in %<target%> attribute, "
@@ -2442,15 +2228,14 @@ fold_builtin_cpu (tree fndecl, tree *args)
tree final;
unsigned int field_val = 0;
- unsigned int NUM_ARCH_NAMES
- = sizeof (arch_names_table) / sizeof (struct _arch_names_table);
- for (i = 0; i < NUM_ARCH_NAMES; i++)
- if (strcmp (arch_names_table[i].name,
- TREE_STRING_POINTER (param_string_cst)) == 0)
+ for (i = 0; i < num_arch_names; i++)
+ if (processor_alias_table[i].model != 0
+ && strcmp (processor_alias_table[i].name,
+ TREE_STRING_POINTER (param_string_cst)) == 0)
break;
- if (i == NUM_ARCH_NAMES)
+ if (i == num_arch_names)
{
error ("parameter to builtin not valid: %s",
TREE_STRING_POINTER (param_string_cst));
@@ -2458,7 +2243,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
}
field = TYPE_FIELDS (__processor_model_type);
- field_val = arch_names_table[i].model;
+ field_val = processor_alias_table[i].model;
/* CPU types are stored in the next field. */
if (field_val > M_CPU_TYPE_START
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 5d0ea16a0bb..e1775ff0b5d 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2498,6 +2498,8 @@ const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
#include "insn-attr-common.h"
+#include "common/config/i386/i386-cpuinfo.h"
+
class pta
{
public:
@@ -2505,10 +2507,13 @@ public:
const enum processor_type processor;
const enum attr_cpu schedule;
const wide_int_bitmask flags;
+ const int model;
+ const enum feature_priority priority;
};
extern const pta processor_alias_table[];
extern int const pta_size;
+extern unsigned int const num_arch_names;
#endif
#endif
--
2.26.2
