Hello, This patch modifies the MVE scalar shift RTL patterns. The current patterns have wrong constraints and predicates due to which the values returned from MVE scalar shift instructions are overwritten in the code-gen.
example:
$ cat x.c
#include "arm_mve.h"
int32_t foo(int64_t acc, int shift)
{
return sqrshrl_sat48 (acc, shift);
}
Code-gen before applying this patch:
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve -mfloat-abi=hard -O2 -S
$ cat x.s
foo:
push {r4, r5}
sqrshrl r0, r1, #48, r2 ----> (a)
mov r0, r4 ----> (b)
pop {r4, r5}
bx lr
Code-gen after applying this patch:
foo:
sqrshrl r0, r1, #48, r2
bx lr
In the current compiler the return value (r0) from sqrshrl (a) is getting
overwritten by the mov statement (b).
This patch fixes above issue.
Please refer to M-profile Vector Extension (MVE) intrinsics [1]for more details.
[1]
https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
Regression tested on arm-none-eabi and found no regressions.
Ok for master and gcc-10 branch?
Thanks,
Srinath.
gcc/ChangeLog:
2020-06-12 Srinath Parvathaneni <srinath.parvathan...@arm.com>
* config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate
and constraint of all the operands.
(mve_sqrshrl_sat<supf>_di): Likewise.
(mve_uqrshl_si): Likewise.
(mve_sqrshr_si): Likewise.
(mve_uqshll_di): Likewise.
(mve_urshrl_di): Likewise.
(mve_uqshl_si): Likewise.
(mve_urshr_si): Likewise.
(mve_sqshl_si): Likewise.
(mve_srshr_si): Likewise.
(mve_srshrl_di): Likewise.
(mve_sqshll_di): Likewise.
* config/arm/predicates.md (arm_low_register_operand): Define.
gcc/testsuite/ChangeLog:
2020-06-12 Srinath Parvathaneni <srinath.parvathan...@arm.com>
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: New test.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.
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