[committed]i386: Fix zero/sign extend expanders [PR95229]

[Uros Bizjak via Gcc-patches]

2020-05-20  Uroš Bizjak  <ubiz...@gmail.com>

gcc/ChangeLog:
    PR target/95229
    * config/i386/sse.md (<code>v8qiv8hi2): Use
    simplify_gen_subreg instead of simplify_subreg.
    (<code>v8qiv8si2): Ditto.
    (<code>v4qiv4si2): Ditto.
    (<code>v4hiv4si2): Ditto.
    (<code>v8qiv8di2): Ditto.
    (<code>v4qiv4di2): Ditto.
    (<code>v2qiv2di2): Ditto.
    (<code>v4hiv4di2): Ditto.
    (<code>v2hiv2di2): Ditto.
    (<code>v2siv2di2): Ditto.

gcc/testsuite/ChangeLog:
    PR target/95229
    * g++.target/i386/pr95229.C: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3348424ba4c..3368d86c1e1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2020-05-20  Uroš Bizjak  <ubiz...@gmail.com>
+
+       PR target/95229
+       * config/i386/sse.md (<code>v8qiv8hi2): Use
+       simplify_gen_subreg instead of simplify_subreg.
+       (<code>v8qiv8si2): Ditto.
+       (<code>v4qiv4si2): Ditto.
+       (<code>v4hiv4si2): Ditto.
+       (<code>v8qiv8di2): Ditto.
+       (<code>v4qiv4di2): Ditto.
+       (<code>v2qiv2di2): Ditto.
+       (<code>v4hiv4di2): Ditto.
+       (<code>v2hiv2di2): Ditto.
+       (<code>v2siv2di2): Ditto.
+
 2020-05-20  Uroš Bizjak  <ubiz...@gmail.com>
 
        PR target/95238
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9bf4361384a..c831543b4e9 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17408,7 +17408,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V16QImode, operands[1], V8QImode, 0);
+      operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
       emit_insn (gen_sse4_1_<code>v8qiv8hi2 (operands[0], operands[1]));
       DONE;
     }
@@ -17485,7 +17485,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V16QImode, operands[1], V8QImode, 0);
+      operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
       emit_insn (gen_avx2_<code>v8qiv8si2 (operands[0], operands[1]));
       DONE;
     }
@@ -17548,7 +17548,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V16QImode, operands[1], V4QImode, 0);
+      operands[1] = simplify_gen_subreg (V16QImode, operands[1], V4QImode, 0);
       emit_insn (gen_sse4_1_<code>v4qiv4si2 (operands[0], operands[1]));
       DONE;
     }
@@ -17640,7 +17640,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V8HImode, operands[1], V4HImode, 0);
+      operands[1] = simplify_gen_subreg (V8HImode, operands[1], V4HImode, 0);
       emit_insn (gen_sse4_1_<code>v4hiv4si2 (operands[0], operands[1]));
       DONE;
     }
@@ -17698,7 +17698,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V16QImode, operands[1], V8QImode, 0);
+      operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
       emit_insn (gen_avx512f_<code>v8qiv8di2 (operands[0], operands[1]));
       DONE;
     }
@@ -17759,7 +17759,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V16QImode, operands[1], V8QImode, 0);
+      operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0);
       emit_insn (gen_avx2_<code>v4qiv4di2 (operands[0], operands[1]));
       DONE;
     }
@@ -17785,7 +17785,7 @@
          (match_operand:V2QI 1 "register_operand")))]
   "TARGET_SSE4_1"
 {
-  operands[1] = simplify_subreg (V16QImode, operands[1], V2QImode, 0);
+  operands[1] = simplify_gen_subreg (V16QImode, operands[1], V2QImode, 0);
   emit_insn (gen_sse4_1_<code>v2qiv2di2 (operands[0], operands[1]));
   DONE;
 })
@@ -17857,7 +17857,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V8HImode, operands[1], V4HImode, 0);
+      operands[1] = simplify_gen_subreg (V8HImode, operands[1], V4HImode, 0);
       emit_insn (gen_avx2_<code>v4hiv4di2 (operands[0], operands[1]));
       DONE;
     }
@@ -17918,7 +17918,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V8HImode, operands[1], V2HImode, 0);
+      operands[1] = simplify_gen_subreg (V8HImode, operands[1], V2HImode, 0);
       emit_insn (gen_sse4_1_<code>v2hiv2di2 (operands[0], operands[1]));
       DONE;
     }
@@ -18008,7 +18008,7 @@
 {
   if (!MEM_P (operands[1]))
     {
-      operands[1] = simplify_subreg (V4SImode, operands[1], V2SImode, 0);
+      operands[1] = simplify_gen_subreg (V4SImode, operands[1], V2SImode, 0);
       emit_insn (gen_sse4_1_<code>v2siv2di2 (operands[0], operands[1]));
       DONE;
     }
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d62db054a15..9d04b2d4b14 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-20  Uroš Bizjak  <ubiz...@gmail.com>
+
+       PR target/95229
+       * g++.target/i386/pr95229.C: New test.
+
 2020-05-20  Mark Eggleston  <markeggles...@gcc.gnu.org>
 
        PR fortran/39695
diff --git a/gcc/testsuite/g++.target/i386/pr95229.C 
b/gcc/testsuite/g++.target/i386/pr95229.C
new file mode 100644
index 00000000000..edf5aa4389e
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr95229.C
@@ -0,0 +1,24 @@
+// PR target/95229
+// { dg-do compile }
+// { dg-options "-O3 -march=znver1" }
+
+struct a {
+  unsigned long long b;
+  unsigned long long c;
+};
+
+class {
+public:
+  a d;
+} e;
+
+struct f {
+  unsigned g;
+  unsigned h;
+  void i();
+};
+
+void f::i() {
+  e.d.b += g;
+  e.d.c += h;
+}