This patch fixes a bug in which 8 and 16-bit vector shifts used the
wrong kind of extend, thus causing wrong results. It was simply a
thinko in the insn code, so easily fixed.
Andrew
P.S. Apologies for the "work-in-progress" tag on the commit subject.
Obviously that was meant to be removed, but I didn't notice it until
after the push. :-(
WIP amdgcn: use unsigned extend for lshiftrt
This fixes a wrong-code logic error in a previous patch.
Detected by gcc.c-torture/execute/pr53645-2.c.
2020-05-15 Andrew Stubbs <a...@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index a43d6b6c6f3..d31fe5063b9 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2113,7 +2113,7 @@
""
{
enum {ashift, lshiftrt, ashiftrt};
- bool unsignedp = (<code> == ashift || <code> == ashiftrt);
+ bool unsignedp = (<code> == lshiftrt);
rtx insi1 = gen_reg_rtx (<VnSI>mode);
rtx insi2 = gen_reg_rtx (<VnSI>mode);
rtx outsi = gen_reg_rtx (<VnSI>mode);