[committed] Fix a couple more instruction length issues on the H8 port

[Jeff Law via Gcc-patches]

And another case were the H8 port had the wrong lengths which resulted in using 
a
short branch instead of the necessary long branch and the short branch going off
into never-never land.   It usually "worked" anyway, but if addresses in the C
runtime line up just right we'd get a fault.

I know we're close to an RC, but this seems safe enough given it just hits the 
H8
port and only the H8SX variant and only corrects the length of two relatively
uncommon instructions.

Installing on the trunk momentarily.

Jeff

commit 392aa7d7adfbd84253121d2ef779bf3c627e8d0b
Author: Jeff Law <l...@torsion.usersys.redhat.com>
Date:   Wed Apr 29 10:19:22 2020 -0400

        Fix some testsuite failures for H8/SX multilibs where short branches 
where used when long branches were necessary.
    
            * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
            division instructions are 4 bytes long.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 80064da83ce..a2d4a1b82f4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-29  Jeff Law  <l...@redhat.com>
+
+       * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
+       division instructions are 4 bytes long.
+
 2020-04-29  Jakub Jelinek  <ja...@redhat.com>
 
        PR target/94826
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 3e5cdbeeebe..a86b8ea2074 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1218,7 +1218,7 @@
                  (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
   "TARGET_H8300SX"
   { return <MODE>mode == HImode ? "divu.w\\t%T2,%T0" : "divu.l\\t%S2,%S0"; }
-  [(set_attr "length" "2")])
+  [(set_attr "length" "4")])
 
 (define_insn "div<mode>3"
   [(set (match_operand:HSI 0 "register_operand" "=r")
@@ -1226,7 +1226,7 @@
                 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
   "TARGET_H8300SX"
   { return <MODE>mode == HImode ? "divs.w\\t%T2,%T0" : "divs.l\\t%S2,%S0"; }
-  [(set_attr "length" "2")])
+  [(set_attr "length" "4")])
 
 (define_insn "udivmodqi4"
   [(set (match_operand:QI 0 "register_operand" "=r")