This patch fixes a bug in which the high-part of a 64-bit add doesn't
always merge in the masked lanes properly, depending on register allocation.
Unfortunately I don't have a small reproducer for this one, so there's
no testcase.
Andrew
amdgcn: Fix wrong-code bug in 64-bit masked add
2020-04-24 Andrew Stubbs <a...@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
of high-part.
(add<mode>_sext_dup2_exec): Likewise.
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 0422e153cf3..d3badb4059c 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1497,7 +1497,8 @@
rtx dsthi = gcn_operand_part (<MODE>mode, operands[0], 1);
emit_insn (gen_vec_duplicate<vnsi>_exec
(dsthi, gcn_operand_part (DImode, operands[2], 1),
- gcn_gen_undef (<VnSI>mode), operands[4]));
+ gcn_operand_part (<MODE>mode, operands[3], 1),
+ operands[4]));
emit_insn (gen_addc<vnsi>3_exec
(dsthi, dsthi, const0_rtx, vcc, vcc,
gcn_operand_part (<MODE>mode, operands[3], 1),
@@ -1564,7 +1565,8 @@
rtx dsthi = gcn_operand_part (<MODE>mode, operands[0], 1);
emit_insn (gen_vec_duplicate<vnsi>_exec
(dsthi, gcn_operand_part (DImode, operands[2], 1),
- gcn_gen_undef (<VnSI>mode), operands[4]));
+ gcn_operand_part (<MODE>mode, operands[3], 1),
+ operands[4]));
emit_insn (gen_addc<vnsi>3_exec
(dsthi, dsthi, operands[5], vcc, vcc,
gcn_operand_part (<MODE>mode, operands[3], 1),
