Hi Anton,
Thanks to you and Joel for clarifying the copyright assignment...
> -----Original Message-----
> From: Gcc-patches <gcc-patches-boun...@gcc.gnu.org> On Behalf Of Anton
> Youdkevitch
> Sent: 20 April 2020 19:29
> To: gcc-patches@gcc.gnu.org
> Cc: jo...@marvell.com
> Subject: [PATCH v2] aarch64: Add TX3 machine model
>
> Here is the patch introducing thunderxt311 maching model
> for the scheduler. A name for the new chip was added to the
> list of the names to be recognized as a valid parameter for mcpu
> and mtune flags. The TX2 cost model was reused for TX3.
>
> The previously used "cryptic" name for the command line
> parameter is replaced with the same "thunderxt311" name.
>
> Bootstrapped on AArch64.
>
> 2020-04-20 Anton Youdkevitch <anton.youdkevi...@bell-sw.com>
>
> * config/aarch64/aarch64-cores.def: Add the chip name.
> * config/aarch64/aarch64-tune.md: Regenerated.
> * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip.
> * gcc/config/aarch64/thunderx3t11.md: New file: add the new
> machine model for the scheduler
> * gcc/config/aarch64/aarch64.md: Include the new model.
No "gcc/" in the path here.
Also, please add an entry in the documentation in doc/invoke.texi for the new
option.
>
> ---
> gcc/config/aarch64/aarch64-cores.def | 3 +
> gcc/config/aarch64/aarch64-tune.md | 2 +-
> gcc/config/aarch64/aarch64.c | 27 +
> gcc/config/aarch64/aarch64.md | 1 +
> gcc/config/aarch64/thunderx3t11.md | 686 +++++++++++++++
> 5 files changed, 718 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index ea9b98b..ece6c34 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -95,6 +95,9 @@ AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AA
/* Cavium ('C') cores. */
AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)
+/* Cavium ('??') cores (TX3). */
+AARCH64_CORE("thunderx3t11", thunderx3t11, thunderx3t11, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx3t11, 0x43, 0x0b8, 0x0a)
+
I appreciate this is early CPU enablement and documentation is not always
ready, but would it be better to use a "Marvell cores" comment above that
entry? Up to you.
The more important thing is the architecture features enabled. The entry here
means it's an Armv8.1-a CPU (with crypto).
>From what I can find on the Internet [1] this CPU has Armv8.3-a features. Can
>you please double-check that and update the flags here, if necessary?
It would be a shame to miss out on architecture enablement for
-mcpu=thunderx3t11 due to a flag mismatch.
Thanks,
Kyrill
[1]
https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor
