In one place we open-code a special case of this pattern into the
more specific sub<GPI>3_compare1_imm, and miss this special case
in other places. Centralize that special case into an expander.
* config/aarch64/aarch64.md (*sub<GPI>3_compare1): Rename
from sub<GPI>3_compare1.
(sub<GPI>3_compare1): New expander.
(usubv<GPI>4): Use aarch64_plus_operand for operand2.
* config/aarch64/aarch64.c (aarch64_expand_subvti): Remove
call to gen_subdi3_compare1_imm.
---
gcc/config/aarch64/aarch64.c | 11 ++---------
gcc/config/aarch64/aarch64.md | 24 +++++++++++++++++++++---
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4af562a81ea..ce306a10de6 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -20797,16 +20797,9 @@ aarch64_expand_subvti (rtx op0, rtx low_dest, rtx
low_in1,
}
else
{
- if (aarch64_plus_immediate (low_in2, DImode))
- emit_insn (gen_subdi3_compare1_imm (low_dest, low_in1, low_in2,
- GEN_INT (-INTVAL (low_in2))));
- else
- {
- low_in2 = force_reg (DImode, low_in2);
- emit_insn (gen_subdi3_compare1 (low_dest, low_in1, low_in2));
- }
- high_in2 = force_reg (DImode, high_in2);
+ emit_insn (gen_subdi3_compare1 (low_dest, low_in1, low_in2));
+ high_in2 = force_reg (DImode, high_in2);
if (unsigned_p)
emit_insn (gen_usubdi3_carryinC (high_dest, high_in1, high_in2));
else
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c7c4d1dd519..728c63bd8d6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2966,13 +2966,12 @@
(define_expand "usubv<mode>4"
[(match_operand:GPI 0 "register_operand")
(match_operand:GPI 1 "aarch64_reg_or_zero")
- (match_operand:GPI 2 "aarch64_reg_or_zero")
+ (match_operand:GPI 2 "aarch64_plus_operand")
(label_ref (match_operand 3 "" ""))]
""
{
emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[1], operands[2]));
aarch64_gen_unlikely_cbranch (LTU, CCmode, operands[3]);
-
DONE;
})
@@ -3119,7 +3118,7 @@
[(set_attr "type" "alus_imm")]
)
-(define_insn "sub<mode>3_compare1"
+(define_insn "*sub<mode>3_compare1"
[(set (reg:CC CC_REGNUM)
(compare:CC
(match_operand:GPI 1 "aarch64_reg_or_zero" "rkZ")
@@ -3131,6 +3130,25 @@
[(set_attr "type" "alus_sreg")]
)
+(define_expand "sub<mode>3_compare1"
+ [(parallel
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (match_operand:GPI 1 "aarch64_reg_or_zero")
+ (match_operand:GPI 2 "aarch64_plus_operand")))
+ (set (match_operand:GPI 0 "register_operand")
+ (minus:GPI (match_dup 1) (match_dup 2)))])]
+ ""
+{
+ if (CONST_SCALAR_INT_P (operands[2]))
+ {
+ emit_insn (gen_sub<mode>3_compare1_imm
+ (operands[0], operands[1], operands[2],
+ GEN_INT (-INTVAL (operands[2]))));
+ DONE;
+ }
+})
+
(define_peephole2
[(set (match_operand:GPI 0 "aarch64_general_reg")
(minus:GPI (match_operand:GPI 1 "aarch64_reg_or_zero")
--
2.20.1
