* config/aarch64/aarch64.md (absti2): New.
---
gcc/config/aarch64/aarch64.md | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index cf716f815a1..4a30d4cca93 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3521,6 +3521,35 @@
}
)
+(define_expand "absti2"
+ [(match_operand:TI 0 "register_operand")
+ (match_operand:TI 1 "register_operand")]
+ ""
+ {
+ rtx lo_op1 = gen_lowpart (DImode, operands[1]);
+ rtx hi_op1 = gen_highpart (DImode, operands[1]);
+ rtx lo_tmp = gen_reg_rtx (DImode);
+ rtx hi_tmp = gen_reg_rtx (DImode);
+ rtx x, cc;
+
+ emit_insn (gen_negdi_carryout (lo_tmp, lo_op1));
+ emit_insn (gen_subdi3_carryin_cmp (hi_tmp, const0_rtx, hi_op1));
+
+ cc = gen_rtx_REG (CC_NZmode, CC_REGNUM);
+ x = gen_rtx_GE (VOIDmode, cc, const0_rtx);
+ x = gen_rtx_IF_THEN_ELSE (DImode, x, lo_tmp, lo_op1);
+ emit_insn (gen_rtx_SET (lo_tmp, x));
+
+ x = gen_rtx_GE (VOIDmode, cc, const0_rtx);
+ x = gen_rtx_IF_THEN_ELSE (DImode, x, hi_tmp, hi_op1);
+ emit_insn (gen_rtx_SET (hi_tmp, x));
+
+ emit_move_insn (gen_lowpart (DImode, operands[0]), lo_tmp);
+ emit_move_insn (gen_highpart (DImode, operands[0]), hi_tmp);
+ DONE;
+ }
+)
+
(define_insn "neg<mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r,w")
(neg:GPI (match_operand:GPI 1 "register_operand" "r,w")))]
--
2.20.1
