Hi Srinath,
> -----Original Message-----
> From: Srinath Parvathaneni <srinath.parvathan...@arm.com>
> Sent: 23 March 2020 17:45
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
> Subject: [PATCH v2][ARM][GCC][14x]: MVE ACLE whole vector left shift with
> carry intrinsics.
>
> Hello Kyrill,
>
> Following patch is the rebased version of v1.
> (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-
> November/534344.html
>
> ####
> Hello,
>
> This patch supports following MVE ACLE whole vector left shift with carry
> intrinsics.
>
> vshlcq_m_s8, vshlcq_m_s16, vshlcq_m_s32, vshlcq_m_u8, vshlcq_m_u16,
> vshlcq_m_u32.
>
> Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more
> details.
> [1] https://developer.arm.com/architectures/instruction-sets/simd-
> isas/helium/mve-intrinsics
>
> Regression tested on arm-none-eabi and found no regressions.
>
> Ok for trunk?
Thanks, I've pushed this patch to master.
Kyrill
>
> Thanks,
> Srinath.
>
> gcc/ChangeLog:
>
> 2019-11-08 Srinath Parvathaneni <srinath.parvathan...@arm.com>
> Andre Vieira <andre.simoesdiasvie...@arm.com>
> Mihail Ionescu <mihail.ione...@arm.com>
>
> * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
> (vshlcq_m_u8): Likewise.
> (vshlcq_m_s16): Likewise.
> (vshlcq_m_u16): Likewise.
> (vshlcq_m_s32): Likewise.
> (vshlcq_m_u32): Likewise.
> (__arm_vshlcq_m_s8): Define intrinsic.
> (__arm_vshlcq_m_u8): Likewise.
> (__arm_vshlcq_m_s16): Likewise.
> (__arm_vshlcq_m_u16): Likewise.
> (__arm_vshlcq_m_s32): Likewise.
> (__arm_vshlcq_m_u32): Likewise.
> (vshlcq_m): Define polymorphic variant.
> * config/arm/arm_mve_builtins.def
> (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
> Use builtin qualifier.
> (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
> * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define
> RTL pattern.
> (mve_vshlcq_m_carry_<supf><mode>): Likewise.
> (mve_vshlcq_m_<supf><mode>): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> 2019-11-08 Srinath Parvathaneni <srinath.parvathan...@arm.com>
> Andre Vieira <andre.simoesdiasvie...@arm.com>
> Mihail Ionescu <mihail.ione...@arm.com>
>
> * gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: New test.
> * gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise.
>
>
> ############### Attachment also inlined for ease of reply
> ###############
>
>
> diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index
> f2d80ee636003ac58f70ddc25db15e129e228906..14b6ec857bffd85b67c781f5
> 54faffde1b2abc6b 100644
> --- a/gcc/config/arm/arm_mve.h
> +++ b/gcc/config/arm/arm_mve.h
> @@ -2546,6 +2546,12 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
> #define urshrl(__p0, __p1) __arm_urshrl(__p0, __p1) #define lsll(__p0, __p1)
> __arm_lsll(__p0, __p1) #define asrl(__p0, __p1) __arm_asrl(__p0, __p1)
> +#define vshlcq_m_s8(__a, __b, __imm, __p) __arm_vshlcq_m_s8(__a,
> +__b, __imm, __p) #define vshlcq_m_u8(__a, __b, __imm, __p)
> +__arm_vshlcq_m_u8(__a, __b, __imm, __p) #define vshlcq_m_s16(__a,
> +__b, __imm, __p) __arm_vshlcq_m_s16(__a, __b, __imm, __p) #define
> +vshlcq_m_u16(__a, __b, __imm, __p) __arm_vshlcq_m_u16(__a, __b,
> +__imm, __p) #define vshlcq_m_s32(__a, __b, __imm, __p)
> +__arm_vshlcq_m_s32(__a, __b, __imm, __p) #define vshlcq_m_u32(__a,
> +__b, __imm, __p) __arm_vshlcq_m_u32(__a, __b, __imm, __p)
> #endif
>
> /* For big-endian, GCC's vector indices are reversed within each 64 bits @@
> -16671,6 +16677,60 @@ __arm_srshr (int32_t value, const int shift)
> return __builtin_mve_srshr_si (value, shift); }
>
> +__extension__ extern __inline int8x16_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vshlcq_m_s8 (int8x16_t __a, uint32_t * __b, const int __imm,
> +mve_pred16_t __p) {
> + int8x16_t __res = __builtin_mve_vshlcq_m_vec_sv16qi (__a, *__b,
> +__imm, __p);
> + *__b = __builtin_mve_vshlcq_m_carry_sv16qi (__a, *__b, __imm, __p);
> + return __res;
> +}
> +
> +__extension__ extern __inline uint8x16_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vshlcq_m_u8 (uint8x16_t __a, uint32_t * __b, const int __imm,
> +mve_pred16_t __p) {
> + uint8x16_t __res = __builtin_mve_vshlcq_m_vec_uv16qi (__a, *__b,
> +__imm, __p);
> + *__b = __builtin_mve_vshlcq_m_carry_uv16qi (__a, *__b, __imm, __p);
> + return __res;
> +}
> +
> +__extension__ extern __inline int16x8_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vshlcq_m_s16 (int16x8_t __a, uint32_t * __b, const int __imm,
> +mve_pred16_t __p) {
> + int16x8_t __res = __builtin_mve_vshlcq_m_vec_sv8hi (__a, *__b, __imm,
> +__p);
> + *__b = __builtin_mve_vshlcq_m_carry_sv8hi (__a, *__b, __imm, __p);
> + return __res;
> +}
> +
> +__extension__ extern __inline uint16x8_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vshlcq_m_u16 (uint16x8_t __a, uint32_t * __b, const int __imm,
> +mve_pred16_t __p) {
> + uint16x8_t __res = __builtin_mve_vshlcq_m_vec_uv8hi (__a, *__b,
> +__imm, __p);
> + *__b = __builtin_mve_vshlcq_m_carry_uv8hi (__a, *__b, __imm, __p);
> + return __res;
> +}
> +
> +__extension__ extern __inline int32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vshlcq_m_s32 (int32x4_t __a, uint32_t * __b, const int __imm,
> +mve_pred16_t __p) {
> + int32x4_t __res = __builtin_mve_vshlcq_m_vec_sv4si (__a, *__b, __imm,
> +__p);
> + *__b = __builtin_mve_vshlcq_m_carry_sv4si (__a, *__b, __imm, __p);
> + return __res;
> +}
> +
> +__extension__ extern __inline uint32x4_t __attribute__
> +((__always_inline__, __gnu_inline__, __artificial__))
> +__arm_vshlcq_m_u32 (uint32x4_t __a, uint32_t * __b, const int __imm,
> +mve_pred16_t __p) {
> + uint32x4_t __res = __builtin_mve_vshlcq_m_vec_uv4si (__a, *__b,
> +__imm, __p);
> + *__b = __builtin_mve_vshlcq_m_carry_uv4si (__a, *__b, __imm, __p);
> + return __res;
> +}
> +
> #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
>
> __extension__ extern __inline void
> @@ -27485,6 +27545,16 @@ extern void *__ARM_undef;
> int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_n_u8
> (__ARM_mve_coerce(__p0, uint32_t), p1, p2), \
> int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_wb_u8
> (__ARM_mve_coerce(__p0, uint32_t *), p1, p2));})
>
> +#define vshlcq_m(p0,p1,p2,p3) __arm_vshlcq_m(p0,p1,p2,p3) #define
> +__arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
> + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
> + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_m_s8
> +(__ARM_mve_coerce(__p0, int8x16_t), p1, p2, p3), \
> + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_m_s16
> +(__ARM_mve_coerce(__p0, int16x8_t), p1, p2, p3), \
> + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_m_s32
> +(__ARM_mve_coerce(__p0, int32x4_t), p1, p2, p3), \
> + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_m_u8
> +(__ARM_mve_coerce(__p0, uint8x16_t), p1, p2, p3), \
> + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_m_u16
> +(__ARM_mve_coerce(__p0, uint16x8_t), p1, p2, p3), \
> + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_m_u32
> +(__ARM_mve_coerce(__p0, uint32x4_t), p1, p2, p3));})
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/gcc/config/arm/arm_mve_builtins.def
> b/gcc/config/arm/arm_mve_builtins.def
> index
> 9379927ae509c1b4fb70e7cbbad40bf645284714..2fb975944b9fdac9de4b5a1
> bec3962be410637f1 100644
> --- a/gcc/config/arm/arm_mve_builtins.def
> +++ b/gcc/config/arm/arm_mve_builtins.def
> @@ -890,3 +890,7 @@ VAR1 (UQSHL, urshr_, si)
> VAR1 (UQSHL, urshrl_, di)
> VAR1 (UQSHL, uqshl_, si)
> VAR1 (UQSHL, uqshll_, di)
> +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_vec_s,
> v16qi, v8hi,
> +v4si)
> +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_carry_s,
> v16qi, v8hi,
> +v4si)
> +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_vec_u,
> v16qi, v8hi,
> +v4si)
> +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_carry_u,
> v16qi,
> +v8hi, v4si)
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index
> ce98e35763107844a70377fbc3e9921bf055b0cb..fc35820ad57d3e87de9f30a1
> 8d58d9002145bb27 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -215,8 +215,8 @@
> VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U
> VSBCIQ_M_S
> VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S
> VADCIQ_U VADCIQ_M_U
> VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q
> SRSHRL SRSHR
> - URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64
> - UQRSHLL_48 SQRSHRL_64 SQRSHRL_48])
> + URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64
> VSHLCQ_M_U
> + UQRSHLL_48 SQRSHRL_64 SQRSHRL_48
> VSHLCQ_M_S])
>
> (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
> (V4SF "V4SI")])
> @@ -394,7 +394,8 @@
> (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s")
> (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
> (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
> - (UQRSHLL_64 "64") (UQRSHLL_48 "48")])
> + (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s")
> + (VSHLCQ_M_U "u")])
>
> (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
> (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
> @@ -659,6 +660,7 @@ (define_int_iterator VADCQ_M [VADCQ_M_U
> VADCQ_M_S]) (define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
> (define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
> +(define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U])
>
> (define_insn "*mve_mov<mode>"
> [(set (match_operand:MVE_types 0 "nonimmediate_operand"
> "=w,w,r,w,w,r,w,Us") @@ -11149,3 +11151,57 @@
> "TARGET_HAVE_MVE"
> "sqshll%?\\t%Q1, %R1, %2"
> [(set_attr "predicable" "yes")])
> +
> +;;
> +;; [vshlcq_m_u vshlcq_m_s]
> +;;
> +(define_expand "mve_vshlcq_m_vec_<supf><mode>"
> + [(match_operand:MVE_2 0 "s_register_operand")
> + (match_operand:MVE_2 1 "s_register_operand")
> + (match_operand:SI 2 "s_register_operand")
> + (match_operand:SI 3 "mve_imm_32")
> + (match_operand:HI 4 "vpr_register_operand")
> + (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] "TARGET_HAVE_MVE"
> +{
> + rtx ignore_wb = gen_reg_rtx (SImode);
> + emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb,
> operands[1],
> + operands[2], operands[3],
> + operands[4]));
> + DONE;
> +})
> +
> +(define_expand "mve_vshlcq_m_carry_<supf><mode>"
> + [(match_operand:SI 0 "s_register_operand")
> + (match_operand:MVE_2 1 "s_register_operand")
> + (match_operand:SI 2 "s_register_operand")
> + (match_operand:SI 3 "mve_imm_32")
> + (match_operand:HI 4 "vpr_register_operand")
> + (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] "TARGET_HAVE_MVE"
> +{
> + rtx ignore_vec = gen_reg_rtx (<MODE>mode);
> + emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0],
> + operands[1], operands[2],
> + operands[3], operands[4]));
> + DONE;
> +})
> +
> +(define_insn "mve_vshlcq_m_<supf><mode>"
> + [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
> + (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
> + (match_operand:SI 3 "s_register_operand" "1")
> + (match_operand:SI 4 "mve_imm_32" "Rf")
> + (match_operand:HI 5 "vpr_register_operand" "Up")]
> + VSHLCQ_M))
> + (set (match_operand:SI 1 "s_register_operand" "=r")
> + (unspec:SI [(match_dup 2)
> + (match_dup 3)
> + (match_dup 4)
> + (match_dup 5)]
> + VSHLCQ_M))
> + ]
> + "TARGET_HAVE_MVE"
> + "vpst\;vshlct\t%q0, %1, %4"
> + [(set_attr "type" "mve_move")
> + (set_attr "length" "8")])
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..c4c77f2559c22bb58a9b501
> d1a2a35dea44b8865
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c
> @@ -0,0 +1,23 @@
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int16x8_t
> +foo (int16x8_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m_s16 (a, b, 32, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> +
> +int16x8_t
> +foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m (a, b, 32, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..20cfd09c82dcdd19bcd6aac
> 66fe2bbe280bf7ec6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c
> @@ -0,0 +1,23 @@
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int32x4_t
> +foo (int32x4_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m_s32 (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> +
> +int32x4_t
> +foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..33dde10e4a8c048de6efb57
> e51d9b9744381f034
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c
> @@ -0,0 +1,23 @@
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +int8x16_t
> +foo (int8x16_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m_s8 (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> +
> +int8x16_t
> +foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..2bf69f0c465e1887043a1b5
> 9d4402ac9d127ab2a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c
> @@ -0,0 +1,23 @@
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint16x8_t
> +foo (uint16x8_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m_u16 (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> +
> +uint16x8_t
> +foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..e6650302ea713b472f3d1ec
> a14a351be8d030745
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c
> @@ -0,0 +1,23 @@
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint32x4_t
> +foo (uint32x4_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m_u32 (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> +
> +uint32x4_t
> +foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..95857f09371d1920213c720
> 22e2e3547d1e18ef3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c
> @@ -0,0 +1,23 @@
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O2" } */
> +
> +#include "arm_mve.h"
> +
> +uint8x16_t
> +foo (uint8x16_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m_u8 (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
> +
> +uint8x16_t
> +foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p) {
> + return vshlcq_m (a, b, 1, p);
> +}
> +
> +/* { dg-final { scan-assembler "vpst" } } */
> +/* { dg-final { scan-assembler "vshlct" } } */
