Hi! On Fri, Mar 20, 2020 at 07:42:29PM -0700, Richard Henderson via Gcc-patches wrote: > @@ -2382,7 +2382,7 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, > rtx y, > cc_mode = CC_SWPmode; > cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); > emit_set_insn (cc_reg, t); > - return cc_reg; > + return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx); > } > } > > @@ -18506,7 +18506,8 @@ aarch64_expand_compare_and_swap (rtx operands[]) > > emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem, > newval, mod_s)); > - cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); > + x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode); > + PUT_MODE (x, SImode);
Maybe this stuff would be simpler (and more obviously correct) if it was more explicit CC_REGNUM is a fixed register, and the code would use it directly everywhere? (Something for stage1 I suppose, if you / the aarch people want to do this at all :-) ) This patch does look correct to me, fwiw. Segher
